From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FDB0275B16; Wed, 22 Oct 2025 21:11:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761167479; cv=none; b=qn8ovFLylWHNWUuwFeCS6rz96hOfUdGYDziqwPe85psAhkaARp7Q22doyLlr4LGRLLXTkLcPNIqMwn9eVVIO/DGuqoj4sfBVYMIDVarq/Z6kwCcvZKChSS8Ak7k5qcLlmI0p2InndvJq+00tjfG0daoutPrtaZ0UncUcgf+iVT8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761167479; c=relaxed/simple; bh=5v3JRmduY4uSzLf2Pqm6596Of3Jc6oNa3Sp1BFVrPsc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Rdd5W7oC5JxEmAO0FEcUN4NKMvPHLNB3Hvw+NFG6+jXaicPLYezaP3VhWPzYdVtlUnXgz/JCaN78WyUxuP0SkOdykxWkranRVk15x3/JH+D1qMMnfb8S8d56WDSApGr2c7jHOQipDvkpgvFsnm2H+m6k7qsHB2JrD//MbMoQj6E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WB/NSEOY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WB/NSEOY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 578E7C4CEE7; Wed, 22 Oct 2025 21:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761167478; bh=5v3JRmduY4uSzLf2Pqm6596Of3Jc6oNa3Sp1BFVrPsc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=WB/NSEOYaZfqO71RaPt4ZWYdN0blDNxWfW5ICS4fnS9/Stg8tNvDA58HxOwxxfAop 6hilG6zy+ngXSW5OHpCRTxNenF9Bk2EaGFRCumPTjrRK/bVON+bnvy/p0jMxSCxSLz Mp+CQpC8F2aarMsxM/M65yF0VX2LxhP4WqDUOqiQqQxpBBwSLDBsOAGAEp/+f54G0J 5gfATau19beB423OmBeJDw9m3Jlk4q89eSCMKQ4jChXPVDrj46xZpnq4bMGDdW6jjZ TIcUJFiK3RcYlJnhG+XHlTjtlGrXivlL71exLBuObtDML9tzLkoDNFK+ey2dSEnLdw wIQpY+RrFrnDw== Date: Wed, 22 Oct 2025 22:11:12 +0100 From: Conor Dooley To: Jonathan Cameron Cc: Catalin Marinas , linux-cxl@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, Dan Williams , "H . Peter Anvin" , Peter Zijlstra , Andrew Morton , james.morse@arm.com, Will Deacon , Davidlohr Bueso , linuxarm@huawei.com, Yushan Wang , Lorenzo Pieralisi , Mark Rutland , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Andy Lutomirski , Dave Jiang Subject: Re: [PATCH v4 3/6] lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Message-ID: <20251022-tried-alright-752fa98ff086@spud> References: <20251022113349.1711388-1-Jonathan.Cameron@huawei.com> <20251022113349.1711388-4-Jonathan.Cameron@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="Vn2cL8c0hs3HiHri" Content-Disposition: inline In-Reply-To: <20251022113349.1711388-4-Jonathan.Cameron@huawei.com> --Vn2cL8c0hs3HiHri Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Oct 22, 2025 at 12:33:46PM +0100, Jonathan Cameron wrote: > From: Yicong Yang >=20 > ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION provides the mechanism for > invalidating certain memory regions in a cache-incoherent manner. Current= ly > this is used by NVDIMM and CXL memory drivers in cases where it is > necessary to flush all data from caches by physical address range. >=20 > In some architectures these operations are supported by system components > that may become available only later in boot as they are either present > on a discoverable bus, or via a firmware description of an MMIO interface > (e.g. ACPI DSDT). Provide a framework to handle this case. >=20 > Architectures can opt in for this support via > CONFIG_GENERIC_CPU_CACHE_MAINTENANCE >=20 > Add a registration framework. Each driver provides an ops structure and > the first op is Write Back and Invalidate by PA Range. The driver may > over invalidate. >=20 > An optional completion check operation is also provided. If present > that should be called to ensure that the action has finished. >=20 > When multiple agents are present in the system each should register with > this framework and the core code will issue the invalidate to all of them > before checking for completion on each. This is done to avoid need for > filtering in the core code which can become complex when interleave, > potentially across different cache coherency hardware is going on, so it > is easier to tell everyone and let those who don't care do nothing. >=20 > Signed-off-by: Yicong Yang > Co-developed-by: Jonathan Cameron > Signed-off-by: Jonathan Cameron Acked-by: Conor Dooley I'm fine with this stuff. I do wonder though, have you actually encountered systems with the multiple "agents" or is that something theoretical? --Vn2cL8c0hs3HiHri Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaPlIcAAKCRB4tDGHoIJi 0ilcAQCnVKkCAStY/FbYOAkfI+W/JVlX+Y1Vm+WSmJKzsDcbvwD/WDlSH0CF9gAy unvtdkqI/cCeZqx8cis9fpSarDvOjQY= =Xs5l -----END PGP SIGNATURE----- --Vn2cL8c0hs3HiHri--