Re: [RESEND v13 10/25] cxl/pci: Update RAS handler interfaces to also support CXL Ports

Alison Schofield
2025-11-11T08:17:49Z

On Tue, Nov 04, 2025 at 11:02:50AM -0600, Terry Bowman wrote:
> CXL PCIe Port Protocol Error handling support will be added to the
> CXL drivers in the future. In preparation, rename the existing
> interfaces to support handling all CXL PCIe Port Protocol Errors.
>
> The driver's RAS support functions currently rely on a 'struct
> cxl_dev_state' type parameter, which is not available for CXL Port
> devices. However, since the same CXL RAS capability structure is
> needed across most CXL components and devices, a common handling
> approach should be adopted.
>
> To accommodate this, update the __cxl_handle_cor_ras() and
> __cxl_handle_ras() functions to use a `struct device` instead of
> `struct cxl_dev_state`.
>
> No functional changes are introduced.
>
> [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>
> ---
>
> Changes in v12->v13:
> - Added Ben's review-by
> ---
> drivers/cxl/core/core.h | 15 ++++++---------
> drivers/cxl/core/ras.c | 12 ++++++------
> drivers/cxl/core/ras_rch.c | 4 ++--
> 3 files changed, 14 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index c30ab7c25a92..1a419b35fa59 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -7,6 +7,7 @@
> #include <linux/pci.h>
> #include <cxl/mailbox.h>
> #include <linux/rwsem.h>
> +#include <linux/pci.h>

Duplicate include above.

snip