Re: [RESEND v13 02/25] PCI/CXL: Introduce pcie_is_cxl()

dan.j.williams
2025-11-19T23:34:36Z

Bowman, Terry wrote:
>
>
> On 11/18/2025 9:19 PM, dan.j.williams@intel.com wrote:
> > Terry Bowman wrote:
> >> CXL and AER drivers need the ability to identify CXL devices.
> >>
> >> Introduce set_pcie_cxl() with logic checking for CXL.mem or CXL.cache
> >> status in the CXL Flexbus DVSEC status register. The CXL Flexbus DVSEC
> >> presence is used because it is required for all the CXL PCIe devices.[1]
> >>
> >> Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL
> >> CXL.cache and CXl.mem status.
> >>
> >> In the case the device is an EP or USP, call set_pcie_cxl() on behalf of
> >> the parent downstream device. Once a device is created there is
> >> possibilty the parent training or CXL state was updated as well. This
> >> will make certain the correct parent CXL state is cached.
> >>
> >> Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'.
> >>
> >> [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended
> >> Capability (DVSEC) ID Assignment, Table 8-2
> >>
> >> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> >> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> >> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> >> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >> Reviewed-by: Alejandro Lucero <alucerop@amd.com>
> >> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> >>
> >> ---
> >>
> >> Changes in v12->v13:
> >> - Add Ben's "reviewed-by"
> >>
> >> Changes in v11->v12:
> >> - Add review-by for Alejandro
> >> - Add comment in set_pcie_cxl() explaining why updating parent status.
> >>
> >> Changes in v10->v11:
> >> - Amend set_pcie_cxl() to check for Upstream Port's and EP's parent
> >> downstream port by calling set_pcie_cxl(). (Dan)
> >> - Retitle patch: 'Add' -> 'Introduce'
> >> - Add check for CXL.mem and CXL.cache (Alejandro, Dan)
> > [..]
> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> >> index 0ce98e18b5a8..63124651f865 100644
> >> --- a/drivers/pci/probe.c
> >> +++ b/drivers/pci/probe.c
> >> @@ -1709,6 +1709,33 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
> >> dev->is_thunderbolt = 1;
> >> }
> >>
> >> +static void set_pcie_cxl(struct pci_dev *dev)
> >> +{
> >> + struct pci_dev *parent;
> >> + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
> >> + PCI_DVSEC_CXL_FLEXBUS_PORT);
> >> + if (dvsec) {
> >> + u16 cap;
> >> +
> >> + pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET, &cap);
> >> +
> >> + dev->is_cxl = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK, cap) ||
> >> + FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK, cap);
> >> + }
> >> +
> >> + if (!pci_is_pcie(dev) ||
> >> + !(pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
> >> + pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM))
> >> + return;
> > Why are downstream ports excluded?
> I thought we only need to check the upstream 'parent' if dev is an EP
> or USP as those are the only PCIe types in CXL that interface directly
> to the upstream dport device.

Yes, but in all cases the device upstream of an endpoint or an upstream
port is a PCI_EXP_TYPE_ROOT_PORT or PCI_EXP_TYPE_DOWNSTREAM device. So I
do not understand why this function needs to make any exclusions.

> And its the upstream dport device that must  be checked to ensure it
> has the correct is_cxl setting.

...but it will never have the correct is_cxl setting because that 'if
()' statement precludes the update.

> Do I need to update is_cxl for USP in the case of DSP-USP topology?

I think the only change needed is drop that early return 'if ()'
statement altogether.