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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 21:41:25.8076 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba2b8cdf-1ad1-44da-0ffe-08de216b10b2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB59.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8451 Add a function for getting common CXL.cache information. This information will be stored in the struct cxl_cache_state member (cstate) of struct cxl_dev_state for easy access by endpoint drivers. Signed-off-by: Ben Cheatham --- drivers/cxl/core/pci.c | 53 ++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 13 +++++++++++ drivers/cxl/cxlcache.h | 7 ++++++ drivers/cxl/cxlpci.h | 4 ++++ 4 files changed, 77 insertions(+) create mode 100644 drivers/cxl/cxlcache.h diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 18825e1505d6..5b1cace8fc0f 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1258,3 +1259,55 @@ int cxl_port_get_possible_dports(struct cxl_port *port) return ctx.count; } +EXPORT_SYMBOL_NS_GPL(cxl_port_get_possible_dports, "CXL"); + +/** + * cxl_accel_read_cache_info - Get the CXL cache information of a CXL cache device + * @cxlds: CXL device state associated with cache device + * + * Returns 0 and populates the struct cxl_cache_state member of @cxlds on + * success, error otherwise. + */ +int cxl_accel_read_cache_info(struct cxl_dev_state *cxlds) +{ + struct cxl_cache_state *cstate = &cxlds->cstate; + struct pci_dev *pdev; + int dvsec, rc; + u16 cap, cap2; + + if (!dev_is_pci(cxlds->dev)) + return -EINVAL; + pdev = to_pci_dev(cxlds->dev); + + dvsec = cxlds->cxl_dvsec; + + rc = pci_read_config_word(pdev, dvsec + CXL_DVSEC_CAP_OFFSET, &cap); + if (rc) + return rc; + + if (!(cap & CXL_DVSEC_CACHE_CAPABLE)) + return -ENXIO; + + rc = pci_read_config_word(pdev, dvsec + CXL_DVSEC_CAP2_OFFSET, &cap2); + if (rc) + return rc; + + /* CXL 3.2 8.1.3.7 DVSEC CXL Capability2 for encoding */ + switch (FIELD_GET(CXL_DVSEC_CACHE_UNIT_MASK, cap2)) { + case 1: + cstate->unit = 64 * SZ_1K; + break; + case 2: + cstate->unit = SZ_1M; + break; + default: + return -ENXIO; + } + + cstate->size = FIELD_GET(CXL_DVSEC_CACHE_SIZE_MASK, cap2) * cstate->unit; + if (!cstate->size) + return -ENXIO; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_accel_read_cache_info, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 1950cf3d5399..259d806fb3e3 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -759,6 +759,17 @@ struct cxl_dpa_info { int nr_partitions; }; + +/** + * struct cxl_cache_state - State of a device's CXL cache + * @size: Size of cache in bytes + * @unit: Unit size of cache in bytes + */ +struct cxl_cache_state { + u64 size; + u32 unit; +}; + /** * struct cxl_dev_state - The driver device state * @@ -779,6 +790,7 @@ struct cxl_dpa_info { * @serial: PCIe Device Serial Number * @type: Generic Memory Class device or Vendor Specific Memory device * @cxl_mbox: CXL mailbox context + * @cstate: CXL cache state and capabilities * @cxlfs: CXL features context */ struct cxl_dev_state { @@ -795,6 +807,7 @@ struct cxl_dev_state { u64 serial; enum cxl_devtype type; struct cxl_mailbox cxl_mbox; + struct cxl_cache_state cstate; #ifdef CONFIG_CXL_FEATURES struct cxl_features_state *cxlfs; #endif diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h new file mode 100644 index 000000000000..8f8597755947 --- /dev/null +++ b/drivers/cxl/cxlcache.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __CXL_CACHE_H__ +#define __CXL_CACHE_H__ +#include "cxl.h" + +int cxl_accel_read_cache_info(struct cxl_dev_state *cxlds); +#endif diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 7ae621e618e7..18230e4f677c 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -17,10 +17,14 @@ /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ #define CXL_DVSEC_PCIE_DEVICE 0 #define CXL_DVSEC_CAP_OFFSET 0xA +#define CXL_DVSEC_CACHE_CAPABLE BIT(0) #define CXL_DVSEC_MEM_CAPABLE BIT(2) #define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4) #define CXL_DVSEC_CTRL_OFFSET 0xC #define CXL_DVSEC_MEM_ENABLE BIT(2) +#define CXL_DVSEC_CAP2_OFFSET 0x16 +#define CXL_DVSEC_CACHE_UNIT_MASK GENMASK(3, 0) +#define CXL_DVSEC_CACHE_SIZE_MASK GENMASK(15, 8) #define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) #define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) #define CXL_DVSEC_MEM_INFO_VALID BIT(0) -- 2.51.1