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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB52.mail.protection.outlook.com (10.167.241.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.13 via Frontend Transport; Tue, 11 Nov 2025 21:41:36 +0000 Received: from ausbcheatha02.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 11 Nov 2025 13:41:36 -0800 From: Ben Cheatham To: CC: Subject: [PATCH 04/17] cxl/core: Add CXL.cache device struct Date: Tue, 11 Nov 2025 15:40:19 -0600 Message-ID: <20251111214032.8188-5-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251111214032.8188-1-Benjamin.Cheatham@amd.com> References: <20251111214032.8188-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|BN5PR12MB9461:EE_ X-MS-Office365-Filtering-Correlation-Id: 3deba67e-fafb-45a0-d39f-08de216b1710 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 21:41:36.4937 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3deba67e-fafb-45a0-d39f-08de216b1710 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9461 Add a new CXL.cache device (struct cxl_cachedev) that is the cache analogue to struct cxl_memdev. This device will be created by endpoint vendor-specific drivers to enable and manage the cache capabilities of the endpoint. Signed-off-by: Ben Cheatham --- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/cachedev.c | 95 +++++++++++++++++++++++++++++++++++++ drivers/cxl/core/port.c | 3 ++ drivers/cxl/cxl.h | 3 ++ drivers/cxl/cxlcache.h | 25 ++++++++++ drivers/cxl/private.h | 4 ++ 6 files changed, 131 insertions(+) create mode 100644 drivers/cxl/core/cachedev.c diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 5ad8fef210b5..94db05d1f351 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -9,6 +9,7 @@ cxl_core-y := port.o cxl_core-y += pmem.o cxl_core-y += regs.o cxl_core-y += memdev.o +cxl_core-y += cachedev.o cxl_core-y += mbox.o cxl_core-y += pci.o cxl_core-y += hdm.o diff --git a/drivers/cxl/core/cachedev.c b/drivers/cxl/core/cachedev.c new file mode 100644 index 000000000000..5693a63baa9b --- /dev/null +++ b/drivers/cxl/core/cachedev.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2025 Advanced Micro Devices, Inc. */ +#include +#include + +#include "../cxlcache.h" +#include "private.h" + +static DEFINE_IDA(cxl_cachedev_ida); + +static void cxl_cachedev_release(struct device *dev) +{ + struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev); + + ida_free(&cxl_cachedev_ida, cxlcd->id); + kfree(cxlcd); +} + +static void cxl_cachedev_unregister(void *dev) +{ + struct cxl_cachedev *cxlcd = dev; + + cxlcd->cxlds = NULL; + device_del(&cxlcd->dev); + put_device(&cxlcd->dev); +} + +static char *cxl_cachedev_devnode(const struct device *dev, umode_t *mode, + kuid_t *uid, kgid_t *gid) +{ + return kasprintf(GFP_KERNEL, "cxl/%s", dev_name(dev)); +} + +static const struct device_type cxl_cachedev_type = { + .name = "cxl_cachedev", + .release = cxl_cachedev_release, + .devnode = cxl_cachedev_devnode, +}; + +bool is_cxl_cachedev(const struct device *dev) +{ + return dev->type == &cxl_cachedev_type; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_cachedev, "CXL"); + +static struct lock_class_key cxl_cachedev_key; + +struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds) +{ + struct device *dev; + int rc; + + struct cxl_cachedev *cxlcd __free(kfree) = + kzalloc(sizeof(*cxlcd), GFP_KERNEL); + if (!cxlcd) + return ERR_PTR(-ENOMEM); + + rc = ida_alloc(&cxl_cachedev_ida, GFP_KERNEL); + if (rc < 0) + return ERR_PTR(rc); + + cxlcd->id = rc; + cxlcd->depth = -1; + cxlcd->cxlds = cxlds; + cxlds->cxlcd = cxlcd; + cxlcd->endpoint = ERR_PTR(-ENXIO); + + dev = &cxlcd->dev; + device_initialize(dev); + lockdep_set_class(&dev->mutex, &cxl_cachedev_key); + dev->parent = cxlds->dev; + dev->bus = &cxl_bus_type; + dev->type = &cxl_cachedev_type; + device_set_pm_not_required(dev); + + return_ptr(cxlcd); +} +EXPORT_SYMBOL_NS_GPL(cxl_cachedev_alloc, "CXL"); + +struct cxl_cachedev *devm_cxl_cachedev_add_or_reset(struct device *host, + struct cxl_cachedev *cxlcd) +{ + int rc; + + rc = device_add(&cxlcd->dev); + if (rc) + return ERR_PTR(rc); + + rc = devm_add_action_or_reset(host, cxl_cachedev_unregister, cxlcd); + if (rc) + return ERR_PTR(rc); + + return cxlcd; +} +EXPORT_SYMBOL_NS_GPL(devm_cxl_cachedev_add_or_reset, "CXL"); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 8128fd2b5b31..603cf862e311 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +78,8 @@ static int cxl_device_id(const struct device *dev) return CXL_DEVICE_REGION; if (dev->type == &cxl_pmu_type) return CXL_DEVICE_PMU; + if (is_cxl_cachedev(dev)) + return CXL_DEVICE_ACCELERATOR; return 0; } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 259d806fb3e3..4cf8ca3a2494 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -779,6 +779,7 @@ struct cxl_cache_state { * * @dev: The device associated with this CXL state * @cxlmd: The device representing the CXL.mem capabilities of @dev + * @cxlcd: The device representing the CXL.cache capabilities of @dev * @reg_map: component and ras register mapping parameters * @regs: Parsed register blocks * @cxl_dvsec: Offset to the PCIe device DVSEC @@ -796,6 +797,7 @@ struct cxl_cache_state { struct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; + struct cxl_cachedev *cxlcd; struct cxl_register_map reg_map; struct cxl_regs regs; int cxl_dvsec; @@ -982,6 +984,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv); #define CXL_DEVICE_PMEM_REGION 7 #define CXL_DEVICE_DAX_REGION 8 #define CXL_DEVICE_PMU 9 +#define CXL_DEVICE_ACCELERATOR 10 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") #define CXL_MODALIAS_FMT "cxl:t%d" diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h index 8f8597755947..24ec8dddefe7 100644 --- a/drivers/cxl/cxlcache.h +++ b/drivers/cxl/cxlcache.h @@ -3,5 +3,30 @@ #define __CXL_CACHE_H__ #include "cxl.h" +/** + * struct cxl_cachedev - CXL bus object representing a cache-capable CXL device + * @dev: driver core device object + * @cxlds: device state backing this device + * @endpoint: connection to the CXL port topology for this device + * @ops: caller specific probe routine + * @id: id number of this cachedev instance + * @depth: endpoint port depth in hierarchy + */ +struct cxl_cachedev { + struct device dev; + struct cxl_dev_state *cxlds; + struct cxl_port *endpoint; + const struct cxl_dev_ops *ops; + int id; + int depth; +}; + +static inline struct cxl_cachedev *to_cxl_cachedev(struct device *dev) +{ + return container_of(dev, struct cxl_cachedev, dev); +} + +bool is_cxl_cachedev(const struct device *dev); + int cxl_accel_read_cache_info(struct cxl_dev_state *cxlds); #endif diff --git a/drivers/cxl/private.h b/drivers/cxl/private.h index ff517452e735..25e6bce2457f 100644 --- a/drivers/cxl/private.h +++ b/drivers/cxl/private.h @@ -12,4 +12,8 @@ #define __CXL_PRIVATE_H__ int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_dport *parent_dport); + +struct cxl_cachedev *cxl_cachedev_alloc(struct cxl_dev_state *cxlds); +struct cxl_cachedev *devm_cxl_cachedev_add_or_reset(struct device *host, + struct cxl_cachedev *cxlcd); #endif /* __CXL_PRIVATE_H__ */ -- 2.51.1