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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB58.mail.protection.outlook.com (10.167.241.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.13 via Frontend Transport; Tue, 11 Nov 2025 21:42:24 +0000 Received: from ausbcheatha02.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 11 Nov 2025 13:42:24 -0800 From: Ben Cheatham To: CC: Subject: [PATCH 08/17] cxl/core: Update devm_cxl_enumerate_ports() Date: Tue, 11 Nov 2025 15:40:23 -0600 Message-ID: <20251111214032.8188-9-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251111214032.8188-1-Benjamin.Cheatham@amd.com> References: <20251111214032.8188-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB58:EE_|IA1PR12MB8190:EE_ X-MS-Office365-Filtering-Correlation-Id: bc9774b0-d27c-4434-0c64-08de216b33c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 21:42:24.6762 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc9774b0-d27c-4434-0c64-08de216b33c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB58.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8190 Update devm_cxl_enumerate_ports() to handle cxl_cachedev devices. After this commit cxl_cachedev's will be added to the CXL port hierarchy, but immediately fail endpoint port probe. Endpoint port probe will be updated to allow cxl cache devices in a following commit. Signed-off-by: Ben Cheatham --- drivers/cxl/cache.c | 16 ++++++ drivers/cxl/core/port.c | 109 ++++++++++++++++++++++++++-------------- drivers/cxl/cxl.h | 3 +- drivers/cxl/mem.c | 2 +- drivers/cxl/port.c | 3 ++ 5 files changed, 94 insertions(+), 39 deletions(-) diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c index 6f410fae9437..630452d53acc 100644 --- a/drivers/cxl/cache.c +++ b/drivers/cxl/cache.c @@ -56,6 +56,22 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_add_cachedev, "CXL"); static int cxl_cache_probe(struct device *dev) { + struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev); + struct cxl_dev_state *cxlds = cxlcd->cxlds; + struct cxl_dport *dport; + int rc; + + rc = devm_cxl_enumerate_ports(dev, cxlds); + if (rc) + return rc; + + struct cxl_port *parent_port __free(put_cxl_port) = + cxl_dev_find_port(dev, &dport); + if (!parent_port) { + dev_err(dev, "CXL port topology not found\n"); + return -ENXIO; + } + return 0; } diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2cccce49e3b4..e79ec29d0bb6 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -844,6 +844,45 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport) &cxl_einj_inject_fops); } +static bool is_cxl_ep_device(struct device *dev) +{ + return is_cxl_memdev(dev) || is_cxl_cachedev(dev); +} + +static int cxl_port_setup_endpoint(struct cxl_port *port) +{ + struct device *uport_dev = port->uport_dev; + struct cxl_dev_state *cxlds; + struct cxl_cachedev *cxlcd; + struct cxl_memdev *cxlmd; + int rc; + + rc = dev_set_name(&port->dev, "endpoint%d", port->id); + if (rc) + return rc; + + /* + * The endpoint driver already enumerated the component and RAS + * registers. Reuse that enumeration while prepping them to be + * mapped by the cxl_port driver. + */ + if (is_cxl_memdev(uport_dev)) { + cxlmd = to_cxl_memdev(uport_dev); + cxlds = cxlmd->cxlds; + + cxlmd->endpoint = port; + } else { + cxlcd = to_cxl_cachedev(uport_dev); + cxlds = cxlcd->cxlds; + + cxlcd->endpoint = port; + } + + port->reg_map = cxlds->reg_map; + port->reg_map.host = &port->dev; + return 0; +} + static int cxl_port_add(struct cxl_port *port, resource_size_t component_reg_phys, struct cxl_dport *parent_dport) @@ -851,22 +890,10 @@ static int cxl_port_add(struct cxl_port *port, struct device *dev __free(put_device) = &port->dev; int rc; - if (is_cxl_memdev(port->uport_dev)) { - struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); - struct cxl_dev_state *cxlds = cxlmd->cxlds; - - rc = dev_set_name(dev, "endpoint%d", port->id); + if (is_cxl_ep_device(port->uport_dev)) { + rc = cxl_port_setup_endpoint(port); if (rc) return rc; - - /* - * The endpoint driver already enumerated the component and RAS - * registers. Reuse that enumeration while prepping them to be - * mapped by the cxl_port driver. - */ - port->reg_map = cxlds->reg_map; - port->reg_map.host = &port->dev; - cxlmd->endpoint = port; } else if (parent_dport) { rc = dev_set_name(dev, "port%d", port->id); if (rc) @@ -1603,7 +1630,8 @@ static int update_decoder_targets(struct device *dev, void *data) DEFINE_FREE(del_cxl_dport, struct cxl_dport *, if (!IS_ERR_OR_NULL(_T)) del_dport(_T)) static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port, - struct device *dport_dev) + struct device *dport_dev, + struct device *ep_dev) { struct cxl_dport *dport; int rc; @@ -1624,6 +1652,10 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port, if (IS_ERR(new_dport)) return new_dport; + /* CXL.cache devices aren't expected to have HDM decoders */ + if (ep_dev && is_cxl_cachedev(ep_dev)) + return no_free_ptr(new_dport); + cxl_switch_parse_cdat(new_dport); if (ida_is_empty(&port->decoder_ida)) { @@ -1655,9 +1687,10 @@ static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev, device_lock_assert(&parent_port->dev); if (!parent_port->dev.driver) { dev_warn(ep_dev, - "port %s:%s:%s disabled, failed to enumerate CXL.mem\n", + "port %s:%s:%s disabled, failed to enumerate CXL.%s\n", dev_name(&parent_port->dev), dev_name(uport_dev), - dev_name(dport_dev)); + dev_name(dport_dev), + is_cxl_memdev(ep_dev) ? "mem" : "cache"); } struct cxl_port *port __free(put_cxl_port) = @@ -1688,10 +1721,10 @@ static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev, } guard(device)(&port->dev); - return cxl_port_add_dport(port, dport_dev); + return cxl_port_add_dport(port, dport_dev, ep_dev); } -static int add_port_attach_ep(struct cxl_memdev *cxlmd, +static int add_port_attach_ep(struct device *ep_dev, struct device *uport_dev, struct device *dport_dev) { @@ -1705,8 +1738,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, * CXL-root 'cxl_port' on a previous iteration, fail for now to * be re-probed after platform driver attaches. */ - dev_dbg(&cxlmd->dev, "%s is a root dport\n", - dev_name(dport_dev)); + dev_dbg(ep_dev, "%s is a root dport\n", dev_name(dport_dev)); return -ENXIO; } @@ -1720,12 +1752,13 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, scoped_guard(device, &parent_port->dev) { parent_dport = cxl_find_dport_by_dev(parent_port, dparent); if (!parent_dport) { - parent_dport = cxl_port_add_dport(parent_port, dparent); + parent_dport = cxl_port_add_dport(parent_port, dparent, + ep_dev); if (IS_ERR(parent_dport)) return PTR_ERR(parent_dport); } - dport = devm_cxl_create_port(&cxlmd->dev, parent_port, + dport = devm_cxl_create_port(ep_dev, parent_port, parent_dport, uport_dev, dport_dev); if (IS_ERR(dport)) { @@ -1736,7 +1769,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, } } - rc = cxl_add_ep(dport, &cxlmd->dev); + rc = cxl_add_ep(dport, ep_dev); if (rc == -EBUSY) { /* * "can't" happen, but this error code means @@ -1756,7 +1789,7 @@ static struct cxl_dport *find_or_add_dport(struct cxl_port *port, device_lock_assert(&port->dev); dport = cxl_find_dport_by_dev(port, dport_dev); if (!dport) { - dport = cxl_port_add_dport(port, dport_dev); + dport = cxl_port_add_dport(port, dport_dev, NULL); if (IS_ERR(dport)) return dport; @@ -1767,9 +1800,8 @@ static struct cxl_dport *find_or_add_dport(struct cxl_port *port, return dport; } -int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) +int devm_cxl_enumerate_ports(struct device *ep_dev, struct cxl_dev_state *cxlds) { - struct device *dev = &cxlmd->dev; struct device *iter; int rc; @@ -1777,12 +1809,15 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) * Skip intermediate port enumeration in the RCH case, there * are no ports in between a host bridge and an endpoint. */ - if (cxlmd->cxlds->rcd) + if (cxlds->rcd) return 0; - rc = devm_add_action_or_reset(&cxlmd->dev, cxl_detach_ep, cxlmd); - if (rc) - return rc; + if (is_cxl_memdev(ep_dev)) { + rc = devm_add_action_or_reset(ep_dev, cxl_detach_ep, + to_cxl_memdev(ep_dev)); + if (rc) + return rc; + } /* * Scan for and add all cxl_ports in this device's ancestry. @@ -1790,7 +1825,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) * attempt fails. */ retry: - for (iter = dev; iter; iter = grandparent(iter)) { + for (iter = ep_dev; iter; iter = grandparent(iter)) { struct device *dport_dev = grandparent(iter); struct device *uport_dev; struct cxl_dport *dport; @@ -1800,18 +1835,18 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) uport_dev = dport_dev->parent; if (!uport_dev) { - dev_warn(dev, "at %s no parent for dport: %s\n", + dev_warn(ep_dev, "at %s no parent for dport: %s\n", dev_name(iter), dev_name(dport_dev)); return -ENXIO; } - dev_dbg(dev, "scan: iter: %s dport_dev: %s parent: %s\n", + dev_dbg(ep_dev, "scan: iter: %s dport_dev: %s parent: %s\n", dev_name(iter), dev_name(dport_dev), dev_name(uport_dev)); struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_uport(uport_dev); if (port) { - dev_dbg(&cxlmd->dev, + dev_dbg(ep_dev, "found already registered port %s:%s\n", dev_name(&port->dev), dev_name(port->uport_dev)); @@ -1829,7 +1864,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) } } - rc = cxl_add_ep(dport, &cxlmd->dev); + rc = cxl_add_ep(dport, ep_dev); /* * If the endpoint already exists in the port's list, @@ -1850,7 +1885,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) return 0; } - rc = add_port_attach_ep(cxlmd, uport_dev, dport_dev); + rc = add_port_attach_ep(ep_dev, uport_dev, dport_dev); /* port missing, try to add parent */ if (rc == -EAGAIN) continue; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 5ef0fb71af91..6c7b8278bec3 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -885,7 +885,8 @@ DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev)) DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) -int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); +int devm_cxl_enumerate_ports(struct device *ep_dev, + struct cxl_dev_state *cxlds); void cxl_bus_rescan(void); void cxl_bus_drain(void); struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index d12c96b68c82..3b230f8c5925 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -104,7 +104,7 @@ static int cxl_mem_probe(struct device *dev) if (rc) return rc; - rc = devm_cxl_enumerate_ports(cxlmd); + rc = devm_cxl_enumerate_ports(dev, cxlds); if (rc) return rc; diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index c2fbdbfe0b6b..efea9b04b323 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -74,6 +74,9 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); int rc; + if (!is_cxl_memdev(port->uport_dev)) + return -EOPNOTSUPP; + /* Cache the data early to ensure is_visible() works */ read_cdat_data(port); cxl_endpoint_parse_cdat(port); -- 2.51.1