From: kernel test robot <lkp@intel.com>
To: smadhavan@nvidia.com, dave@stgolabs.net,
jonathan.cameron@huawei.com, dave.jiang@intel.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dan.j.williams@intel.com,
bhelgaas@google.com, ming.li@zohomail.com, rrichter@amd.com,
Smita.KoralahalliChannabasappa@amd.com,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Cc: oe-kbuild-all@lists.linux.dev, smadhavan@nvidia.com,
vaslot@nvidia.com, vsethi@nvidia.com, sdonthineni@nvidia.com,
vidyas@nvidia.com, mochs@nvidia.com, jsequeira@nvidia.com
Subject: Re: [PATCH v4 06/10] PCI: wire CXL reset prepare/cleanup
Date: Sat, 24 Jan 2026 15:54:10 +0800 [thread overview]
Message-ID: <202601241505.gxL2m9pU-lkp@intel.com> (raw)
In-Reply-To: <20260120222610.2227109-7-smadhavan@nvidia.com>
Hi,
kernel test robot noticed the following build errors:
[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v6.19-rc6]
[cannot apply to next-20260123]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/smadhavan-nvidia-com/cxl-move-DVSEC-defines-to-cxl-pci-header/20260121-071852
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20260120222610.2227109-7-smadhavan%40nvidia.com
patch subject: [PATCH v4 06/10] PCI: wire CXL reset prepare/cleanup
config: openrisc-allmodconfig (https://download.01.org/0day-ci/archive/20260124/202601241505.gxL2m9pU-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260124/202601241505.gxL2m9pU-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601241505.gxL2m9pU-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/cxl/pci.c:1085:6: error: redefinition of 'cxl_is_type2_device'
1085 | bool cxl_is_type2_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~
In file included from drivers/cxl/pci.c:11:
include/linux/pci.h:1476:20: note: previous definition of 'cxl_is_type2_device' with type 'bool(struct pci_dev *)' {aka '_Bool(struct pci_dev *)'}
1476 | static inline bool cxl_is_type2_device(struct pci_dev *dev)
| ^~~~~~~~~~~~~~~~~~~
drivers/cxl/pci.c: In function 'cxl_check_region_driver_bound':
drivers/cxl/pci.c:1102:28: error: 'cxl_region_rwsem' undeclared (first use in this function); did you mean 'cxl_region_ref'?
1102 | guard(rwsem_read)(&cxl_region_rwsem);
| ^~~~~~~~~~~~~~~~
| cxl_region_ref
drivers/cxl/pci.c:1102:28: note: each undeclared identifier is reported only once for each function it appears in
drivers/cxl/pci.c:1103:41: error: 'struct cxl_region' has no member named 'driver'
1103 | if (cxld->region && cxld->region->driver)
| ^~
drivers/cxl/pci.c: In function 'cxl_decoder_kill_region_iter':
drivers/cxl/pci.c:1120:9: error: implicit declaration of function 'cxl_decoder_kill_region_locked'; did you mean 'cxl_decoder_kill_region_iter'? [-Wimplicit-function-declaration]
1120 | cxl_decoder_kill_region_locked(cxled);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| cxl_decoder_kill_region_iter
drivers/cxl/pci.c: In function 'cxl_region_flush_device_caches':
drivers/cxl/pci.c:1187:53: error: 'struct cxl_dev_state' has no member named 'pdev'; did you mean 'dev'?
1187 | if (!target_cxlds || !target_cxlds->pdev)
| ^~~~
| dev
drivers/cxl/pci.c:1190:35: error: 'struct cxl_dev_state' has no member named 'pdev'; did you mean 'dev'?
1190 | if (target_cxlds->pdev != target_pdev)
| ^~~~
| dev
drivers/cxl/pci.c: In function 'cxl_reset_prepare_memdev':
drivers/cxl/pci.c:1231:21: error: 'cxl_region_rwsem' undeclared (first use in this function); did you mean 'cxl_region_ref'?
1231 | down_write(&cxl_region_rwsem);
| ^~~~~~~~~~~~~~~~
| cxl_region_ref
In file included from include/linux/spinlock.h:63,
from include/linux/mmzone.h:8,
from include/linux/gfp.h:7,
from include/linux/mm.h:7,
from arch/openrisc/include/asm/pgalloc.h:20,
from arch/openrisc/include/asm/io.h:18,
from include/linux/io.h:12,
from include/linux/io-64-nonatomic-lo-hi.h:5,
from drivers/cxl/pci.c:4:
drivers/cxl/pci.c: In function 'cxl_reset_cleanup_memdev':
drivers/cxl/pci.c:1265:35: error: 'cxl_region_rwsem' undeclared (first use in this function); did you mean 'cxl_region_ref'?
1265 | if (lockdep_is_held_type(&cxl_region_rwsem, -1))
| ^~~~~~~~~~~~~~~~
include/linux/lockdep.h:253:61: note: in definition of macro 'lockdep_is_held_type'
253 | #define lockdep_is_held_type(lock, r) lock_is_held_type(&(lock)->dep_map, (r))
| ^~~~
drivers/cxl/pci.c: At top level:
>> drivers/cxl/pci.c:1278:5: error: redefinition of 'cxl_reset_prepare_device'
1278 | int cxl_reset_prepare_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/pci.h:1481:19: note: previous definition of 'cxl_reset_prepare_device' with type 'int(struct pci_dev *)'
1481 | static inline int cxl_reset_prepare_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/cxl/pci.c:1303:6: error: redefinition of 'cxl_reset_cleanup_device'
1303 | void cxl_reset_cleanup_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
include/linux/pci.h:1486:20: note: previous definition of 'cxl_reset_cleanup_device' with type 'void(struct pci_dev *)'
1486 | static inline void cxl_reset_cleanup_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
vim +/cxl_reset_prepare_device +1278 drivers/cxl/pci.c
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1268
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1269 /**
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1270 * cxl_reset_prepare_device - Prepare CXL device for reset
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1271 * @pdev: PCI device being reset
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1272 *
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1273 * CXL-reset-specific preparation. Validates memory is offline, flushes
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1274 * device caches, and tears down regions.
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1275 *
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1276 * Returns: 0 on success, -EBUSY if memory online, negative on error
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1277 */
76e9ed09acad72 Srirangan Madhavan 2026-01-20 @1278 int cxl_reset_prepare_device(struct pci_dev *pdev)
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1279 {
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1280 int rc;
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1281
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1282 rc = cxl_reset_prepare_memdev(pdev);
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1283 if (rc) {
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1284 if (rc == -EBUSY)
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1285 dev_err(&pdev->dev,
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1286 "Cannot reset: device has online memory or active regions\n");
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1287 else
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1288 dev_err(&pdev->dev,
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1289 "Failed to prepare device for reset: %d\n", rc);
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1290 return rc;
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1291 }
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1292
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1293 return 0;
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1294 }
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1295 EXPORT_SYMBOL_NS_GPL(cxl_reset_prepare_device, "CXL");
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1296
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1297 /**
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1298 * cxl_reset_cleanup_device - Cleanup after CXL reset
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1299 * @pdev: PCI device that was reset
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1300 *
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1301 * Releases region locks held during reset.
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1302 */
76e9ed09acad72 Srirangan Madhavan 2026-01-20 @1303 void cxl_reset_cleanup_device(struct pci_dev *pdev)
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1304 {
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1305 cxl_reset_cleanup_memdev(pdev);
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1306 }
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1307 EXPORT_SYMBOL_NS_GPL(cxl_reset_cleanup_device, "CXL");
76e9ed09acad72 Srirangan Madhavan 2026-01-20 1308
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2026-01-24 7:55 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-20 22:26 [PATCH v4 0/10] CXL Reset support for Type 2 devices smadhavan
2026-01-20 22:26 ` [PATCH v4 01/10] cxl: move DVSEC defines to cxl pci header smadhavan
2026-01-21 10:31 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 02/10] PCI: switch CXL port DVSEC defines smadhavan
2026-01-21 10:34 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 03/10] cxl: add type 2 helper and reset DVSEC bits smadhavan
2026-01-20 23:27 ` Dave Jiang
2026-01-21 10:45 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 04/10] PCI: add CXL reset method smadhavan
2026-01-21 0:08 ` Dave Jiang
2026-01-21 10:57 ` Jonathan Cameron
2026-01-23 13:54 ` kernel test robot
2026-01-20 22:26 ` [PATCH v4 05/10] cxl: add reset prepare and region teardown smadhavan
2026-01-21 11:09 ` Jonathan Cameron
2026-01-21 21:25 ` Dave Jiang
2026-01-20 22:26 ` [PATCH v4 06/10] PCI: wire CXL reset prepare/cleanup smadhavan
2026-01-21 22:13 ` Dave Jiang
2026-01-22 2:17 ` Srirangan Madhavan
2026-01-22 15:11 ` Dave Jiang
2026-01-24 7:54 ` kernel test robot [this message]
2026-01-20 22:26 ` [PATCH v4 07/10] cxl: add host cache flush and multi-function reset smadhavan
2026-01-21 11:20 ` Jonathan Cameron
2026-01-21 20:27 ` Davidlohr Bueso
2026-01-22 9:53 ` Jonathan Cameron
2026-01-21 22:19 ` Vikram Sethi
2026-01-22 9:40 ` Souvik Chakravarty
[not found] ` <PH7PR12MB9175CDFC163843BB497073CEBD96A@PH7PR12MB9175.namprd12.prod.outlook.com>
2026-01-22 10:31 ` Jonathan Cameron
2026-01-22 19:24 ` Vikram Sethi
2026-01-23 13:13 ` Jonathan Cameron
2026-01-21 23:59 ` Dave Jiang
2026-01-20 22:26 ` [PATCH v4 08/10] cxl: add DVSEC config save/restore smadhavan
2026-01-21 11:31 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 09/10] PCI: save/restore CXL config around reset smadhavan
2026-01-21 22:32 ` Dave Jiang
2026-01-22 10:01 ` Lukas Wunner
2026-01-22 10:47 ` Jonathan Cameron
2026-01-26 22:34 ` Alex Williamson
2026-03-12 18:24 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 10/10] cxl: add HDM decoder and IDE save/restore smadhavan
2026-01-21 11:42 ` Jonathan Cameron
2026-01-22 15:09 ` Dave Jiang
2026-01-21 1:19 ` [PATCH v4 0/10] CXL Reset support for Type 2 devices Alison Schofield
2026-01-22 0:00 ` Bjorn Helgaas
2026-01-27 16:33 ` Alex Williamson
2026-01-27 17:02 ` dan.j.williams
2026-01-27 18:07 ` Vikram Sethi
2026-01-28 3:42 ` dan.j.williams
2026-01-28 12:36 ` Jonathan Cameron
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