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Mon, 26 Jan 2026 17:34:37 -0500 (EST) Date: Mon, 26 Jan 2026 15:34:35 -0700 From: Alex Williamson To: Jonathan Cameron Cc: Lukas Wunner , , , , , , , , , , , , , , , , , , , , , "Terry Bowman" Subject: Re: [PATCH v4 09/10] PCI: save/restore CXL config around reset Message-ID: <20260126153435.5f1557df@shazbot.org> In-Reply-To: <20260122104745.00001fea@huawei.com> References: <20260120222610.2227109-1-smadhavan@nvidia.com> <20260120222610.2227109-10-smadhavan@nvidia.com> <20260122104745.00001fea@huawei.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 22 Jan 2026 10:47:45 +0000 Jonathan Cameron wrote: > On Thu, 22 Jan 2026 11:01:57 +0100 > Lukas Wunner wrote: > > > On Tue, Jan 20, 2026 at 10:26:09PM +0000, smadhavan@nvidia.com wrote: > > > +++ b/drivers/pci/pci.c > > > @@ -4989,6 +4990,11 @@ static int cxl_reset(struct pci_dev *dev, bool probe) > > > if (probe) > > > return 0; > > > > > > + pci_save_state(dev); > > > + rc = cxl_config_save_state(dev, &cxl_state); > > > + if (rc) > > > + pci_warn(dev, "Failed to save CXL config state: %d\n", rc); > > > + > > > > Hm, shouldn't the call to cxl_config_save_state() be moved to > > pci_save_state() (and likewise, cxl_config_restore_state() moved to > > pci_restore_state())? > > > > E.g. when a DPC event occurs, I assume CXL registers need to > > be restored as well on recovery, right? > The CXL spec has some comic language around DPC that basically says > "use with care, DPC trigger will bring down physical link, reset devicestate, > disrupt CXL.cache and CXL.mem traffic". > or in shorter words > 'Good luck' > > If a CXL device undergoes DPC high chance you'll either trigger CXL isolation > which we aren't handing yet in Linux because we aren't convinced software > can really recover form it, or stall a CPU and end up rebooting. > > Maybe we'll one day we'll figure this out. Today turn off DPC on CXL ports! :) Even if we hand-wave that DPC isn't an issue, save/restore of the PCI state happens at a higher level for every other PCI reset method and we're creating inconsistency here. PCI-core includes interfaces for saving PCI state, offloading PCI state as an opaque blob, reloading, and restoring that state, and performing resets without saving and restoring state. This has a couple users, including vfio. If we want similar behavior for CXL type2 devices for a future vfio use case, we shouldn't create unnecessary differentiation here with saving the CXL state separately and making the reset method behave differently. Thanks, Alex