Re: [PATCH v4 0/10] CXL Reset support for Type 2 devices

Alison Schofield
2026-01-21T01:20:04Z

On Tue, Jan 20, 2026 at 10:26:00PM +0000, smadhavan@nvidia.com wrote:
> From: Srirangan Madhavan <smadhavan@nvidia.com>
>
> Hi folks!
>
> This patch series introduces support for the CXL Reset method for CXL
> devices, implementing the reset procedure outlined in CXL Spec [1] v3.2,
> Sections 9.6 and 9.7.

Hi Srirangan,

Following-up on the base commit for this patch. For the cxl subsystem,
a patchset today is expected to be based on 6.19-rc4 (or rc5 or rc6).
We get to that because our cxl/next is based on rc4. We ask folks not
to base on cxl/next because we want to see conflicts between patchsets.

I like to use the base commit option to automatically append it to
the cover letter, but you can just state it in the change log if your
method of sending patches doesn't support that.

With this set, there is something else that you are depending upon.
Please call that out and point to the commits in some way so we can
build on 6.19-rc4 plus those commits plus this patchset.

Thanks!
Alison

>
> v4 changes:
> - Fix CXL reset capability check parentheses warning
> - Gate CXL reset path on CONFIG_CXL_PCI reachability
>
> v3 changes:
> - Restrict CXL reset to Type 2 devices only
> - Add host and device cache flushing for
> * all sibling functions on multi-function devices
> * all sibling devices in a given region
> - Add region teardown and memory online detection before reset
> - Add configuration state save/restore (DVSEC, HDM, IDE)
> - Split the series by subsystem and functional blocks
>
> v2 changes:
> - De-duplicate CXL DVSEC register defines under include/cxl/pci.h
> - Fix style-related issues
>
> v1 changes:
> - Added cover letter and dropped the RFC
>
> The RFC patches can be found here [2]
> v2 patches can be found here [3]
>
> Motivation:
> -----------
> This change is broadly useful for reasons including but not limited to the
> following:
>
> - As support for Type 2 devices [4] is being introduced, more devices will
> require finer-grained reset mechanisms beyond bus-wide reset methods.
>
> - FLR does not affect CXL.cache or CXL.mem protocols, making CXL Reset
> the preferred method in some cases.
>
> - The CXL spec (Sections 7.2.3 Binding and Unbinding, 9.5 FLR) highlights use
> cases like function rebinding and error recovery, where CXL Reset is
> explicitly mentioned.
>
> Change Description:
> -------------------
>
> Patch 1: Move CXL DVSEC defines to the CXL PCI header
> - Consolidate DVSEC register definitions under include/cxl/pci.h
>
> Patch 2: Switch PCI CXL port DVSEC defines
> - Use the shared CXL PCI header in the PCI core
>
> Patch 3: Add Type 2 helper and reset DVSEC bits
> - Add helper to identify Type 2 devices
> - Define DVSEC reset/cache control bits
>
> Patch 4: Add the CXL reset method in the PCI core
> - Implement cxl_reset() method with capability checks and reset sequence
> - Restrict to Type 2 devices
>
> Patch 5: Add reset preparation and region teardown
> - Implement region validation and teardown before reset
> - Add device cache flush for all sibling devices in a given region
>
> Patch 6: Wire CXL reset prepare/cleanup in PCI
> - Call CXL reset prepare/cleanup around the core reset flow
>
> Patch 7: Add host CPU cache flush and multi-function support
> - Add host CPU cache flush (x86: wbinvd, arm64: dcache_clean_inval_poc)
> - Add device cache flush for all sibling functions on multi-function devices
>
> Patch 8: Add DVSEC configuration state save/restore
> - Save/restore DVSEC registers (DEVCTL, DEVCTL2) with CONFIG_LOCK handling
>
> Patch 9: Save/restore CXL config around reset
> - Save PCI and CXL config before reset and restore afterwards
>
> Patch 10: Add HDM decoder and IDE state save/restore
> - Save/restore HDM decoder and IDE register state
>
> The reset sequence: validate device type, check memory offline, tear down
> regions, flush host CPU caches, flush device caches (all functions), save
> config state, initiate reset, wait for completion, restore config state.
>
> Command line to test the CXL reset on a capable device:
> echo cxl_reset > /sys/bus/pci/devices/<pci_device>/reset_method
> echo 1 > /sys/bus/pci/devices/<pci_device>/reset
>
> [1] https://computeexpresslink.org/cxl-specification/
> [2] https://lore.kernel.org/all/20241213074143.374-1-smadhavan@nvidia.com/
> [3] https://lore.kernel.org/all/20250221043906.1593189-1-smadhavan@nvidia.com/
> [4] https://lore.kernel.org/linux-cxl/20251205115248.772945-1-alejandro.lucero-palau@amd.com/
>
> Srirangan Madhavan (10):
> [PATCH v4 1/10] cxl: move DVSEC defines to cxl pci header
> [PATCH v4 2/10] PCI: switch CXL port DVSEC defines
> [PATCH v4 3/10] cxl: add type 2 helper and reset DVSEC bits
> [PATCH v4 4/10] PCI: add CXL reset method
> [PATCH v4 5/10] cxl: add reset prepare and region teardown
> [PATCH v4 6/10] PCI: wire CXL reset prepare/cleanup
> [PATCH v4 7/10] cxl: add host cache flush and multi-function reset
> [PATCH v4 8/10] cxl: add DVSEC config save/restore
> [PATCH v4 9/10] PCI: save/restore CXL config around reset
> [PATCH v4 10/10] cxl: add HDM decoder and IDE save/restore
>
> drivers/cxl/core/pci.c | 1 +
> drivers/cxl/core/regs.c | 8 +
> drivers/cxl/cxl.h | 4 +
> drivers/cxl/cxlpci.h | 53 ---
> drivers/cxl/pci.c | 621 +++++++++++++++++++++++++++++++++-
> drivers/pci/pci.c | 150 +++++++-
> include/cxl/pci.h | 134 ++++++++
> include/linux/pci.h | 21 +-
> include/uapi/linux/pci_regs.h | 5 -
> 9 files changed, 929 insertions(+), 68 deletions(-)
> create mode 100644 include/cxl/pci.h
>
> --
> 2.34.1