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[80.230.34.155]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43617e25683sm1324489f8f.6.2026.02.03.12.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 12:39:25 -0800 (PST) Date: Tue, 3 Feb 2026 15:39:22 -0500 From: "Michael S. Tsirkin" To: Jonathan Cameron Cc: qemu-devel@nongnu.org, Davidlohr Bueso , linuxarm@huawei.com, linux-cxl@vger.kernel.org, Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: Re: [PATCH qemu v5 0/7] hw/cxl: Support Back-Invalidate (+ PCIe Flit mode) Message-ID: <20260203153759-mutt-send-email-mst@kernel.org> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: QamNFit4TF3TqFPU11tFeuIG1DxnQJ6xGm4-jqWpi5g_1770151167 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Jan 09, 2026 at 02:45:04PM +0000, Jonathan Cameron wrote: > Lightly reworked version of Davidlohr's v4. > https://lore.kernel.org/qemu-devel/20251103195209.1319917-1-dave@stgolabs.net/ > > Whilst I have several other series posted for merge this applies fine > to upstream, so no dependencies. > Davidlohr, please check I didn't mess anthing up and perhaps give tags > for the 3 new patches. applying this on top does seem to conflict. let me get rest merged then this can be rebased. > v5 changes: > - Rebase much earlier in the CXL queue as Davidlohr had it beind some stuff > I was carrying that is not ready for upstream just yet. > - Update the CFMWS flags directly as the patch doing restriction control needs > some more thought. > - Bios tables test data updates. > - Don't provide flit mode control for gen_pcie_root_port as we don't need it > for the rest of the series which is all about CXL. > > The following allows support for component basic back invalidation discovery > and config, by exposing the BI routing table and decoder registers. Instead > of going the type2[0] route, this series proposes adding support for type3 > hdm-db, which allows a more direct way of supporting BI in qemu. > > As BI is a dependent on the larger flits introduced in PCIe (and CXL 3.0) > add support for enabling that for CXL components. Negotiation is handled > via an equivalent of what we do for link speed. > > Davidlohr Bueso (3): > hw/pcie: Support enabling flit mode > hw/cxl: Support type3 HDM-DB > hw/cxl: Remove register special_ops->read() > > Ira Weiny (1): > hw/cxl: Refactor component register initialization > > Jonathan Cameron (3): > tests/bios-tables-test: Excluded CEDT.cxl for BI restriction > relaxation. > hw/cxl: Update CXL Fixed Memory Window ACPI description to include > Back Invalidate support. > tests/acpi/cxl: Update CEDT.cxl to allow BI in CFWMS > > docs/system/devices/cxl.rst | 23 +++ > include/hw/cxl/cxl_component.h | 87 +++++++-- > include/hw/cxl/cxl_device.h | 4 + > include/hw/pci-bridge/cxl_upstream_port.h | 1 + > include/hw/pci/pcie.h | 2 +- > include/hw/pci/pcie_port.h | 1 + > hw/acpi/cxl.c | 2 +- > hw/cxl/cxl-component-utils.c | 211 ++++++++++++++++------ > hw/mem/cxl_type3.c | 15 +- > hw/pci-bridge/cxl_downstream.c | 10 +- > hw/pci-bridge/cxl_root_port.c | 11 +- > hw/pci-bridge/cxl_upstream.c | 18 +- > hw/pci-bridge/pci_expander_bridge.c | 2 +- > hw/pci/pcie.c | 23 ++- > tests/data/acpi/x86/q35/CEDT.cxl | Bin 184 -> 184 bytes > 15 files changed, 313 insertions(+), 97 deletions(-) > > -- > 2.48.1