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Tsirkin" CC: , Davidlohr Bueso , , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: Re: [PATCH qemu v5 6/7] hw/cxl: Support type3 HDM-DB Message-ID: <20260204115041.00001755@huawei.com> In-Reply-To: <20260203144122-mutt-send-email-mst@kernel.org> References: <20260109144511.557781-1-Jonathan.Cameron@huawei.com> <20260109144511.557781-7-Jonathan.Cameron@huawei.com> <20260203144122-mutt-send-email-mst@kernel.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: lhrpeml100012.china.huawei.com (7.191.174.184) To dubpeml500005.china.huawei.com (7.214.145.207) > > + } > > + > > + return cregs->cache_mem_registers[offset / 4]; > > case 8: > > qemu_log_mask(LOG_UNIMP, > > "CXL 8 byte cache mem registers not implemented\= n"); > > @@ -118,6 +148,47 @@ static void dumb_hdm_handler(CXLComponentState *cx= l_cstate, hwaddr offset, > > stl_le_p((uint8_t *)cache_mem + offset, value); > > } > > =20 > > +static void bi_handler(CXLComponentState *cxl_cstate, hwaddr offset, > > + uint32_t value) > > +{ > > + ComponentRegisters *cregs =3D &cxl_cstate->crb; > > + uint32_t sts, *cache_mem =3D cregs->cache_mem_registers; > > + bool to_commit =3D false; > > + int type; =20 >=20 > type is declared here... >=20 > > + > > + switch (offset) { > > + case A_CXL_BI_RT_CTRL: > > + to_commit =3D FIELD_EX32(value, CXL_BI_RT_CTRL, COMMIT); > > + if (to_commit) { > > + sts =3D cxl_cache_mem_read_reg(cxl_cstate, > > + R_CXL_BI_RT_STATUS, 4); > > + sts =3D FIELD_DP32(sts, CXL_BI_RT_STATUS, COMMITTED, 0); > > + stl_le_p((uint8_t *)cache_mem + R_CXL_BI_RT_STATUS, sts); > > + type =3D CXL_BISTATE_RT; =20 >=20 > and initialized here >=20 > > + } > > + break; > > + case A_CXL_BI_DECODER_CTRL: > > + to_commit =3D FIELD_EX32(value, CXL_BI_DECODER_CTRL, COMMIT); > > + if (to_commit) { > > + sts =3D cxl_cache_mem_read_reg(cxl_cstate, > > + R_CXL_BI_DECODER_STATUS, 4); > > + sts =3D FIELD_DP32(sts, CXL_BI_DECODER_STATUS, COMMITTED, = 0); > > + stl_le_p((uint8_t *)cache_mem + R_CXL_BI_DECODER_STATUS, s= ts); > > + type =3D CXL_BISTATE_DECODER; =20 >=20 > and here >=20 > > + } > > + break; > > + default: > > + break; > > + } > > + > > + if (to_commit) { > > + cxl_cstate->bi_state[type].last_commit =3D > > + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); =20 >=20 > so there is no way for it to be used uninitialized. >=20 >=20 > However some gcc versions are not smart enough to see that > and they warn: >=20 > https://gitlab.com/mstredhat/qemu/-/jobs/12972572228 >=20 >=20 > ../hw/cxl/cxl-component-utils.c: In function =E2=80=98cxl_cache_mem_write= _reg=E2=80=99: > ../hw/cxl/cxl-component-utils.c:181:48: error: =E2=80=98type=E2=80=99 may= be used uninitialized in this function [-Werror=3Dmaybe-uninitialized] > 181 | cxl_cstate->bi_state[type].last_commit =3D > | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^ > 182 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); > | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > ../hw/cxl/cxl-component-utils.c:153:9: note: =E2=80=98type=E2=80=99 was d= eclared here > 153 | int type; > | ^~~~ > cc1: all warnings being treated as errors >=20 Thanks. I'll set it to 0 at declaration with a comment that it's there to r= esolve a compiler warning (so no one deletes it as a cleanup!) Jonathan