From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
<dave.jiang@intel.com>, Alejandro Lucero <alucerop@amd.com>,
Gregory Price <gourry@gourry.net>
Subject: Re: [PATCH v3 2/3] cxl/region: Factor out interleave ways setup
Date: Mon, 2 Mar 2026 15:26:43 +0000 [thread overview]
Message-ID: <20260302152643.00003027@huawei.com> (raw)
In-Reply-To: <20260228173603.1125109-3-alejandro.lucero-palau@amd.com>
On Sat, 28 Feb 2026 17:36:02 +0000
alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Region creation based on Type3 devices can be triggered from user space
> allowing memory combination through interleaving.
>
> In preparation for kernel driven region creation, that is Type2 drivers
> triggering region creation backed with its advertised CXL memory, factor
> out a common helper from the user-sysfs region setup for interleave ways.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Tested-by: Gregory Price <gourry@gourry.net>
Maybe we should take this opportunity to make ->interleave_ways
unsigned and move all logic to assume this is never negative.
However this is a more minimal change so I'm fine with this and
potentially a future tidy up to make all ways values unsigned.
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
next prev parent reply other threads:[~2026-03-02 15:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-28 17:36 [PATCH v3 0/3] cxl region changes for Type2 support alejandro.lucero-palau
2026-02-28 17:36 ` [PATCH v3 1/3] cxl: Make region type based on endpoint type alejandro.lucero-palau
2026-02-28 17:36 ` [PATCH v3 2/3] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2026-03-02 15:26 ` Jonathan Cameron [this message]
2026-03-03 1:01 ` Alison Schofield
2026-02-28 17:36 ` [PATCH v3 3/3] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2026-03-16 23:57 ` [PATCH v3 0/3] cxl region changes for Type2 support Dave Jiang
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