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Fri, 6 Mar 2026 00:00:32 -0800 From: To: , , , , , , , CC: , , , , , , , , , , , , , , "Srirangan Madhavan" Subject: [PATCH 0/5] PCI/CXL: Save and restore CXL DVSEC and HDM state across resets Date: Fri, 6 Mar 2026 08:00:14 +0000 Message-ID: <20260306080026.116789-1-smadhavan@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002316:EE_|SJ2PR12MB9210:EE_ X-MS-Office365-Filtering-Correlation-Id: 059b5438-c535-49bc-ec64-08de7b56796d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700016|1800799024|13003099007; X-Microsoft-Antispam-Message-Info: F/pgyL8DFObV8vlPLOVedjaA8/3aqVuUQ/tehwJ0Asd49aP0OHydlnaVXXVo5O1cUwXkrJJYZxcTKzu65n7OpXwrsjdivRBmx8cY3wci4juzYrGKnv06vPXsJdet1Lv0DfK8k2Ml+1wHYBJZht7brzY0xW0jrE9xp3+5E1iTgnCEdCncQ0aiocc4F7ln++f9FIl8Jck+dJ/jWKZEKo1O7IvSAC9wiTpMLeH7kDmaziLvQFATm4pNNOwn7fNLwMnm0HJaYmQOX+2Pa6aBytRmvc7eAiZYskCcxlZwCToHXrh2gHxNM8woNijHX7pr5fm8tLRubZc45PNHEoinKWrnSsSTGm68NXtaaMWrlvgvcDcQxeIA5BigjTnndYqQFEopx7FAJGAg3rvr8ZPdBrBVRTCmmWGrsCm/Co0aSELtfUmyqYU6MKLs0s8RTrV+D2pP58KdPSpXlLow1DRQUTqNlzGhBFS11R7fm5nVdzx8zjzVXrrrgaOK89PTuhmj6qDiteP5w4u4NhUqwOJYZmxU4F3otxXONs9m5FVkv+C6q4hcVqfNG4xsegukH5Xeaj9bJ8HPvwKYOz9O9WIeeWFxrdf5F6bRMCObQtv5MVFrI5ozWLloyzi7wjzMSMx29cL2G9no5rtZE8R1htD+mSz/PbQuHQPDS4VWrfs2Wh5VbrTBCHoHejuEVrDV47iwxOyCDnpFORARvO5dI9Sxwj9FfUB3ABuvxhczgfwnGlXPuyvn8Y5KMwurFjIvIGBtSbgHM+mtiOw9wKJhR3XC7g5iJw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700016)(1800799024)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HsKsBzLevroPhccze6MXy4mo3zRonbRWexNjxyf1k9wsYKdx+CcDiTNa/xNsZq7EeNFAOXbYU7vMoYukD/DgJa7wuNkqflA2nTQ26GsePR318c4EnDl/CzYFYluVFo4g3UiPxKj2BZpM6qxT05OEjobidkMufoFAmYlkAEvNtP3LYnT4KP3irKLV7vtWNihwUWbRewAMysNQxHR1ZJ1iu/s1uapnpG4gXbpRCLMruU+2OFgjmdSOXb2zWuJsHp4WYvi3BxADE8pHNd0UIfA508Kz/hvlSB/4x6HMSkaq1ekGLPfw/VPXcydC/N8FvGtkOBfARXTM/vN5USD6oaPuuP6Ft3NI0zTwUS+2SlkhOxxW3hyuj7QKuhvK2msWCW0xmpqeilKBUh7SU5kMdhdboB5FCBRIDfdg1tw/Hv4z3pCe1qcyeSI1PSSUqL4HmGx9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 08:00:46.7479 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 059b5438-c535-49bc-ec64-08de7b56796d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002316.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9210 From: Srirangan Madhavan CXL devices could lose their DVSEC configuration and HDM decoder programming after multiple reset methods (whenever link disable/enable). This means a device that was fully configured — with DVSEC control/range registers set and HDM decoders committed — loses that state after reset. In cases where these are programmed by firmware, downstream drivers are unable to re-initialize the device because CXL memory ranges are no longer mapped. This series adds CXL state save/restore logic to the PCI core so that DVSEC and HDM decoder state is preserved across any PCI reset path that calls pci_save_state() / pci_restore_state(), for a CXL capable device. HDM decoder defines and the cxl_register_map infrastructure are moved from internal CXL driver headers to a new public include/cxl/pci.h, allowing drivers/pci/cxl.c to use them. This layout aligns with Alejandro Lucero's CXL Type-2 device series [1] to minimize conflicts when both land. When he rebases to 7.0-rc2, I can move my changes on top of his. These patches were previously part of the CXL reset series and have been split out [2] to allow independent review and merging. Review feedback on the save/restore portions from v4 has been addressed. Tested on a CXL Type-2 device. DVSEC and HDM state is correctly saved before reset and restored after, with decoder commit confirmed via the COMMITTED status bit. Type-3 device testing is in progress. This series is based on v7.0-rc1. [1] https://lore.kernel.org/linux-cxl/20260201155438.2664640-1-alejandro.lucero-palau@amd.com/ [2] https://lore.kernel.org/linux-cxl/aa8d4f6a-e7bd-4a20-8d34-4376ea314b8f@intel.com/T/#m825c6bdd1934022123807e86d235358a63b08dbc Srirangan Madhavan (5): PCI: Add CXL DVSEC control, lock, and range register definitions cxl: Move HDM decoder and register map definitions to include/cxl/pci.h PCI: Add virtual extended cap save buffer for CXL state PCI: Add cxl DVSEC state save/restore across resets PCI/CXL: Add HDM decoder state save/restore drivers/cxl/cxl.h | 107 +------- drivers/cxl/cxlpci.h | 10 - drivers/pci/Kconfig | 4 + drivers/pci/Makefile | 1 + drivers/pci/cxl.c | 468 ++++++++++++++++++++++++++++++++++ drivers/pci/pci.c | 23 ++ drivers/pci/pci.h | 18 ++ include/cxl/pci.h | 129 ++++++++++ include/uapi/linux/pci_regs.h | 6 + 9 files changed, 650 insertions(+), 116 deletions(-) create mode 100644 drivers/pci/cxl.c create mode 100644 include/cxl/pci.h base-commit: 6de23f81a5e0 -- 2.43.0