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Fri, 6 Mar 2026 18:34:51 -0500 (EST) Date: Fri, 6 Mar 2026 16:32:32 -0700 From: Alex Williamson To: Cc: alex@shazbot.org, , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v5 7/7] Documentation: ABI: Add CXL PCI cxl_reset sysfs attribute Message-ID: <20260306163232.0b9f75a4@shazbot.org> In-Reply-To: <20260306092322.148765-8-smadhavan@nvidia.com> References: <20260306092322.148765-1-smadhavan@nvidia.com> <20260306092322.148765-8-smadhavan@nvidia.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 6 Mar 2026 09:23:22 +0000 wrote: > From: Srirangan Madhavan > > Document the cxl_reset sysfs attribute added to PCI devices that > support CXL Reset. > > Signed-off-by: Srirangan Madhavan > --- > Documentation/ABI/testing/sysfs-bus-pci | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci > index b767db2c52cb..d67c733626b8 100644 > --- a/Documentation/ABI/testing/sysfs-bus-pci > +++ b/Documentation/ABI/testing/sysfs-bus-pci > @@ -174,6 +174,28 @@ Description: > similiar to writing 1 to their individual "reset" file, so use > with caution. > > +What: /sys/bus/pci/devices/.../cxl_reset > +Date: February 2026 > +Contact: linux-cxl@vger.kernel.org > +Description: > + This attribute is only visible when the device advertises > + CXL Reset Capable in the CXL DVSEC Capability register > + (CXL r3.2, section 8.1.3). > + > + Writing 1 to this file triggers a CXL device reset which > + affects CXL.cache and CXL.mem state on all CXL functions > + (i.e. those not listed in the Non-CXL Function Map DVSEC, > + section 8.1.4), not just CXL.io/PCIe state. This is > + separate from the standard PCI reset interface because CXL > + Reset has different scope. > + > + The reset will fail with -EBUSY if any CXL regions using this > + device have drivers bound. Active regions are torn down as > + part of the reset sequence. There's no such test afaict. Thanks, Alex > + > + This attribute is registered by the CXL core when a CXL device > + is discovered, independent of which driver binds the PCI device. > + > What: /sys/bus/pci/devices/.../vpd > Date: February 2008 > Contact: Ben Hutchings > -- > 2.43.0 > >