From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Davidlohr Bueso <dave@stgolabs.net>
Cc: <dave.jiang@intel.com>, <dan.j.williams@intel.com>,
<alison.schofield@intel.com>, <ira.weiny@intel.com>,
<gourry@gourry.net>, <dongjoo.seo1@samsung.com>,
<anisa.su@samsung.com>, <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH 6/6] cxl: Add HDM-DB region creation and sysfs interface
Date: Fri, 20 Mar 2026 16:39:10 +0000 [thread overview]
Message-ID: <20260320163910.00003298@huawei.com> (raw)
In-Reply-To: <20260315202741.3264295-7-dave@stgolabs.net>
On Sun, 15 Mar 2026 13:27:41 -0700
Davidlohr Bueso <dave@stgolabs.net> wrote:
> A single Type 3 device can expose different parts of its memory with different
> coherency semantics. For example, some memory ranges within a Type 3 device
> could be configured as HDM-H, while other memory ranges on the same device
> could be configured as HDM-DB. This allows for flexible memory configuration
> within a single device. As such, coherency models are defined per memory region.
>
> For accelerators (type2), it is expected for the respective drivers to manage
> the HDM-D[B] region creation. For type3, relevant sysfs tunables are provided
> to the user.
>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Seems fine to me, but I'm suffering Friday so don't really trust my
wakefulness enough to tag this version.
prev parent reply other threads:[~2026-03-20 16:39 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-15 20:27 [PATCH 0/6] cxl: Support Back-Invalidate Davidlohr Bueso
2026-03-15 20:27 ` [PATCH 1/6] cxl: Add Back-Invalidate register definitions and structures Davidlohr Bueso
2026-03-19 16:59 ` Jonathan Cameron
2026-03-20 14:57 ` Jonathan Cameron
2026-03-23 22:11 ` Dave Jiang
2026-03-15 20:27 ` [PATCH 2/6] cxl: Add BI register probing and port initialization Davidlohr Bueso
2026-03-20 15:46 ` Jonathan Cameron
2026-03-20 16:19 ` Cheatham, Benjamin
2026-03-23 23:10 ` Dave Jiang
2026-03-15 20:27 ` [PATCH 3/6] cxl/pci: Add Back-Invalidate topology enable/disable Davidlohr Bueso
2026-03-20 16:20 ` Cheatham, Benjamin
2026-03-20 20:52 ` Alison Schofield
2026-03-20 16:27 ` [PATCH 3/6] cxl/pci: Add Back-Invalidate topology enable/disabl Jonathan Cameron
2026-03-24 0:21 ` [PATCH 3/6] cxl/pci: Add Back-Invalidate topology enable/disable Dave Jiang
2026-03-15 20:27 ` [PATCH 4/6] cxl: Wire BI setup and dealloc into device lifecycle Davidlohr Bueso
2026-03-20 16:20 ` Cheatham, Benjamin
2026-03-20 16:29 ` Jonathan Cameron
2026-03-15 20:27 ` [PATCH 5/6] cxl/hdm: Add BI coherency support for endpoint decoders Davidlohr Bueso
2026-03-20 16:20 ` Cheatham, Benjamin
2026-03-15 20:27 ` [PATCH 6/6] cxl: Add HDM-DB region creation and sysfs interface Davidlohr Bueso
2026-03-20 16:39 ` Jonathan Cameron [this message]
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