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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF00020E63.mail.protection.outlook.com (10.167.249.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.17 via Frontend Transport; Wed, 8 Apr 2026 20:33:16 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 8 Apr 2026 15:33:15 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , CC: , Subject: [ndctl PATCH 3/3] test/cxl: Force RAS status in cxl_handle_cor_ras() and cxl_handle_ras() Date: Wed, 8 Apr 2026 15:32:31 -0500 Message-ID: <20260408203231.962206-4-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260408203231.962206-1-terry.bowman@amd.com> References: <20260408203231.962206-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E63:EE_|LV2PR12MB5751:EE_ X-MS-Office365-Filtering-Correlation-Id: a0d4ea3b-b326-405e-b696-08de95ae1069 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|36860700016|376014|921020|22082099003|18002099003|56012099003; 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Provide the means to test protocol errors for all CXL devices in a testing environment. Use 'aer-inject' userspace tool to deliver AER internal error notification which will trigger the CXL driver's RAS handling. Hardcode the status for CE and UCE errors in cxl_handle_ras() and cxl_handle_cor_ras(). Signed-off-by: Terry Bowman --- ...AS-status-in-cxl_handle_cor_ras-and-.patch | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 test/contrib/cxl-aer-einj/patches/0001-test-cxl-Force-RAS-status-in-cxl_handle_cor_ras-and-.patch diff --git a/test/contrib/cxl-aer-einj/patches/0001-test-cxl-Force-RAS-status-in-cxl_handle_cor_ras-and-.patch b/test/contrib/cxl-aer-einj/patches/0001-test-cxl-Force-RAS-status-in-cxl_handle_cor_ras-and-.patch new file mode 100644 index 0000000..d8562cc --- /dev/null +++ b/test/contrib/cxl-aer-einj/patches/0001-test-cxl-Force-RAS-status-in-cxl_handle_cor_ras-and-.patch @@ -0,0 +1,51 @@ +From 1b4054d82a1834e211ef3f284b9f51926db8f060 Mon Sep 17 00:00:00 2001 +From: Terry Bowman +Date: Tue, 7 Apr 2026 16:47:45 -0500 +Subject: [PATCH] test/cxl: Force RAS status in cxl_handle_cor_ras() and + cxl_handle_ras() + +CXL RAS error injection is present for Root Ports but not for other CXL +devices. Provide the means to test protocol errors for all CXL devices +in a testing environment. Use 'aer-inject' userspace tool to deliver AER +internal error notification which will trigger the CXL driver's RAS +handling. Hardcode the status for CE and UCE errors in cxl_handle_ras() +and cxl_handle_cor_ras(). + +Signed-off-by: Terry Bowman +--- + drivers/cxl/core/ras.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c +index 006c6ffc2f56..09ff82973c70 100644 +--- a/drivers/cxl/core/ras.c ++++ b/drivers/cxl/core/ras.c +@@ -183,6 +183,9 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) + } + EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); + ++#define CXL_RAS_UNCORRECTABLE_STATUS_CACHE_ECC 0x1 ++#define CXL_RAS_CORRECTABLE_STATUS_CACHE_ECC 0x1 ++ + void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) + { + void __iomem *addr; +@@ -193,6 +196,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) + + addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; + status = readl(addr); ++ status |= CXL_RAS_CORRECTABLE_STATUS_CACHE_ECC; + if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); +@@ -232,6 +236,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) + + addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; + status = readl(addr); ++ status |= CXL_RAS_UNCORRECTABLE_STATUS_CACHE_ECC; + if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) + return false; + +-- +2.34.1 + -- 2.34.1