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[130.88.198.135]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-447b3d48517sm5205950f8f.5.2026.04.29.06.58.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 06:58:02 -0700 (PDT) From: Joshua Lant To: linux-cxl@vger.kernel.org Cc: qemu-devel@nongnu.org, Jonathan.Cameron@huawei.com, arpit1.kumar@samsung.com, Joshua Lant Subject: [RFC QEMU PATCH 06/10] cxl-upstream-port: Add support for targeting a VCS switch Date: Wed, 29 Apr 2026 14:48:40 +0100 Message-ID: <20260429135717.3048713-7-joshualant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260429135717.3048713-1-joshualant@gmail.com> References: <20260429135717.3048713-1-joshualant@gmail.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Allows an upstream port to be registered on the CLI as a VCS within a cxl-vcs-switch. A VCS is defined as an upstream pci-pci bridge, and a set of downstream virtual pci-pci bridges VPPBs, which form a single Virtual Hierarchy within the switch. Signed-off-by: Joshua Lant --- hw/pci-bridge/cxl_upstream.c | 20 ++++++++++++++++++++ include/hw/pci-bridge/cxl_upstream_port.h | 2 ++ 2 files changed, 22 insertions(+) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index 3fcfc2cde6..a91f721c9e 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -16,6 +16,8 @@ #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" #include "hw/pci-bridge/cxl_upstream_port.h" +#include "hw/cxl/cxl_vcs_switch.h" + /* * Null value of all Fs suggested by IEEE RA guidelines for use of * EU, OUI and CID @@ -346,6 +348,22 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) goto err_cap; } + if (usp->vcs_name && usp->ppb != UINT8_MAX) { + Object *obj = object_resolve_path_component( + object_get_objects_root(), usp->vcs_name); + if (!obj) { + error_setg(errp, "vcs '%s' not found", usp->vcs_name); + goto err_cap; + } + if (!object_dynamic_cast(obj, TYPE_CXL_VCS_SWITCH)) { + error_setg(errp, "'%s' is not a cxl-vcs-switch", usp->vcs_name); + goto err_cap; + } + cxl_vcs_register_usp(CXL_VCS_SWITCH(obj), usp, errp); + if (*errp) + goto err_cap; + } + return; err_cap: @@ -372,6 +390,8 @@ static const Property cxl_upstream_props[] = { DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort, width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", CXLUpstreamPort, flitmode, false), + DEFINE_PROP_STRING("vcs", CXLUpstreamPort, vcs_name), + DEFINE_PROP_UINT8("usppb", CXLUpstreamPort, ppb, UINT8_MAX), }; static void cxl_upstream_class_init(ObjectClass *oc, const void *data) diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h index ce248f3dca..05632286db 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -22,6 +22,8 @@ typedef struct CXLUpstreamPort { DOECap doe_cdat; uint64_t sn; + char *vcs_name; + uint8_t ppb; } CXLUpstreamPort; #endif /* CXL_SUP_H */ -- 2.47.3