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From: Joshua Lant <joshualant@gmail.com>
To: linux-cxl@vger.kernel.org
Cc: jic23@kernel.org, Joshua Lant <joshualant@gmail.com>
Subject: [QEMU PATCH 2/2] cxl_downstream: enable power controller present capability.
Date: Wed, 20 May 2026 15:16:48 +0100	[thread overview]
Message-ID: <20260520141816.3240010-4-joshualant@gmail.com> (raw)
In-Reply-To: <20260520141816.3240010-2-joshualant@gmail.com>

PCI_EXP_SLTCAP_PCP (Power Controller Present) must be set in the DSP's
slot capabilities for PCIe managed hot-remove to complete. Without this
notification from the guest of removal cannot be sent back to the
device.

Fixes: 845f94de78c ("hw/pci-bridge/cxl_upstream: Provide x-speed and x-width properties.")

Signed-off-by: Joshua Lant <joshualant@gmail.com>
---
 hw/pci-bridge/cxl_downstream.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
index ec450d1aa0..6ba6f1aa52 100644
--- a/hw/pci-bridge/cxl_downstream.c
+++ b/hw/pci-bridge/cxl_downstream.c
@@ -228,6 +228,8 @@ static const Property cxl_dsp_props[] = {
     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
                                 width, PCIE_LINK_WIDTH_16),
     DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true),
+    DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
+                    QEMU_PCIE_SLTCAP_PCP_BITNR, true),
 };
 
 static void cxl_dsp_class_init(ObjectClass *oc, const void *data)
-- 
2.47.3


      parent reply	other threads:[~2026-05-20 14:19 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-20 14:16 [QEMU PATCH 0/2] cxl: fixes for hot-removal of devices Joshua Lant
2026-05-20 14:16 ` [QEMU PATCH 1/2] cxl-type3: Properly unmap the memory-backend on device exit Joshua Lant
2026-05-20 14:16 ` Joshua Lant [this message]

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