Re: [PATCH v7 05/11] cxl: Add CXL Device Reset helper

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Read-modify-write of CXL_CTRL2 register accidentally re-triggers self-clearing commands on error paths.
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commit 2cd253f3fe48a32fcac990882cdcc0aac716f026
Author: Srirangan Madhavan <smadhavan@nvidia.com>

cxl: Add CXL Device Reset helper

This commit adds an internal helper for Type 2 CXL functions that support CXL
Reset. The helper disables caching, initiates writeback and reset, waits for
completion, and re-enables caching.

> diff --git a/drivers/cxl/core/reset.c b/drivers/cxl/core/reset.c
> index fc52d3abdb5b4..fdfcc9e825e03 100644
> --- a/drivers/cxl/core/reset.c
> +++ b/drivers/cxl/core/reset.c

[ ... ]

> +static int cxl_reset_update_ctrl2(struct pci_dev *pdev, int dvsec, u16 set,
> +				  u16 clear)
> +{
> +	u16 ctrl2;
> +	int rc;
> +
> +	rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CTRL2, &ctrl2);
> +	if (rc)
> +		return pcibios_err_to_errno(rc);
> +
> +	ctrl2 |= set;
> +	ctrl2 &= ~clear;
> +
> +	rc = pci_write_config_word(pdev, dvsec + PCI_DVSEC_CXL_CTRL2, ctrl2);

[Severity: High]
If a timeout occurs in cxl_reset_disable_cache() while the 
PCI_DVSEC_CXL_INIT_CACHE_WBI command is still in flight, the error path
calls cxl_reset_enable_cache() which relies on this read-modify-write
operation.

Since the hardware operation timed out, the self-clearing command bit might
still be read as 1. Does writing 1 back to this bit here unintentionally
re-trigger the hung hardware operation?

Should self-clearing command bits like PCI_DVSEC_CXL_INIT_CACHE_WBI and
PCI_DVSEC_CXL_INIT_CXL_RST be explicitly masked out from ctrl2 before the
pci_write_config_word() call to prevent this?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260623032453.3404772-1-smadhavan@nvidia.com?part=5