From: Guixin Liu <kanie@linux.alibaba.com>
To: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jic23@kernel.org>,
Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Dan Williams <djbw@kernel.org>, Ira Weiny <iweiny@kernel.org>,
Li Ming <ming.li@zohomail.com>, Robert Richter <rrichter@amd.com>
Cc: linux-cxl@vger.kernel.org, xlpang@linux.alibaba.com,
oliver.yang@linux.alibaba.com
Subject: [PATCH 5/8] cxl/hdm: Fix out of bounds read of the decoder target list
Date: Tue, 11 Aug 2026 19:36:05 +0800 [thread overview]
Message-ID: <20260811113608.2815625-6-kanie@linux.alibaba.com> (raw)
In-Reply-To: <20260811113608.2815625-1-kanie@linux.alibaba.com>
init_hdm_decoder() copies the HDM Decoder Target List register into
cxld->target_map using the decoder's interleave ways as the element count:
union {
u64 value;
unsigned char target_id[8];
} target_list;
...
target_list.value = (hi << 32) + lo;
for (i = 0; i < cxld->interleave_ways; i++)
cxld->target_map[i] = target_list.target_id[i];
The Target List register is 8 bytes wide, i.e. 8 target ports, but
interleave ways comes from the 4-bit Interleave Ways field of the decoder
control register, and eiw_to_ways() maps the valid encodings to 1, 2, 4, 8,
16 (eiw 0-4) and 3, 6, 12 (eiw 8-10). A switch or host bridge decoder found
programmed with 12 or 16 ways therefore reads up to 8 bytes past the
on-stack union.
The region programming path already rejects that configuration in
cxl_port_setup_targets(), 'if (iw > 8 || iw > cxlsd->nr_targets)', but the
enumeration path of a BIOS programmed decoder has no such check.
Reject the decoder instead, consistent with how the neighbouring
eiw_to_ways() and eig_to_granularity() failures are handled: a target list
that cannot describe the interleave is not a configuration the driver can
attach a region to.
Fixes: d17d0540a0db ("cxl/core/hdm: Add CXL standard decoder enumeration to the core")
Signed-off-by: Guixin Liu <kanie@linux.alibaba.com>
---
drivers/cxl/core/hdm.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 0c80b76a5f9b..9d49b48a4456 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -1084,6 +1084,18 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
cxld->interleave_ways, cxld->interleave_granularity);
if (!cxled) {
+ /*
+ * The Target List register only holds
+ * ARRAY_SIZE(target_list.target_id) entries, so a switch
+ * decoder cannot interleave across more ports than that.
+ */
+ if (cxld->interleave_ways > ARRAY_SIZE(target_list.target_id)) {
+ dev_warn(&port->dev,
+ "decoder%d.%d: Interleave ways: %d exceeds target list size\n",
+ port->id, cxld->id, cxld->interleave_ways);
+ return -ENXIO;
+ }
+
lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));
hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));
target_list.value = (hi << 32) + lo;
--
2.43.7
next prev parent reply other threads:[~2026-08-11 11:36 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-11 11:36 [PATCH 0/8] cxl: Assorted fixes Guixin Liu
2026-08-11 11:36 ` [PATCH 1/8] cxl/features: Validate the fwctl RPC input length Guixin Liu
2026-08-11 11:36 ` [PATCH 2/8] cxl/features: Bound the Get Feature output by the user output buffer Guixin Liu
2026-08-11 11:36 ` [PATCH 3/8] cxl/core: Fix dport use-after-free via the einj_inject debugfs file Guixin Liu
2026-08-11 16:03 ` Li Ming
2026-08-12 1:58 ` Guixin Liu
2026-08-11 11:36 ` [PATCH 4/8] cxl/pci: Fix NULL pointer dereference in reset detection Guixin Liu
2026-08-11 11:36 ` Guixin Liu [this message]
2026-08-11 11:36 ` [PATCH 6/8] cxl/cdat: Fix uninitialized stack use in endpoint bandwidth gathering Guixin Liu
2026-08-11 11:36 ` [PATCH 7/8] cxl/mce: Validate the memdev and endpoint before use Guixin Liu
2026-08-11 11:36 ` [PATCH 8/8] cxl/region: Unregister the pmem region bridge on setup failure Guixin Liu
2026-08-11 19:57 ` [PATCH 0/8] cxl: Assorted fixes Alison Schofield
2026-08-12 2:10 ` Guixin Liu
2026-08-12 6:29 ` Richard Cheng
2026-08-12 6:37 ` Guixin Liu
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