From: sashiko-bot@kernel.org
To: penn <engguopeng@buaa.edu.cn>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 1/2] PCI: Add MMIO Capabilities Register Block definitions
Date: Mon, 17 Aug 2026 08:07:16 +0000 [thread overview]
Message-ID: <20260817080716.D1F691F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260817075854.17207-2-engguopeng@buaa.edu.cn>
> From: Penn <engguopeng@buaa.edu.cn>
>
> PCIe r7.0 sec 6.35 defines the MMIO Capabilities Register Block
> (MCAP). It consists of an array header followed by capability headers
> that identify the version, location, size, and vendor of each MMIO
> capability.
>
> Define the MCAP array-header and capability-header registers and their
> fields. These definitions allow subsystem drivers to use the Vendor ID
> along with the Capability ID when capabilities from multiple vendors
> share the same MCAP.
>
> Signed-off-by: Penn <engguopeng@buaa.edu.cn>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260817075854.17207-1-engguopeng@buaa.edu.cn?part=1
next prev parent reply other threads:[~2026-08-17 8:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-17 7:58 [PATCH v2 0/2] PCI/CXL: Distinguish CXL capabilities in MCAP penn
2026-08-17 7:58 ` [PATCH v2 1/2] PCI: Add MMIO Capabilities Register Block definitions penn
2026-08-17 8:07 ` sashiko-bot [this message]
2026-08-17 7:58 ` [PATCH v2 2/2] cxl/core: Skip non-CXL capabilities in MCAP penn
2026-08-17 8:10 ` sashiko-bot
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