From: Junjie Cao <junjie.cao@intel.com>
To: Chen Pei <cp0613@linux.alibaba.com>
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, mst@redhat.com,
imammedo@redhat.com, sunilvl@ventanamicro.com,
sunilvl@oss.qualcomm.com, jic23@kernel.org, pbonzini@redhat.com,
liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,
zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com,
anisinha@redhat.com, dave.jiang@intel.com,
alison.schofield@intel.com, guoren@kernel.org,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
linux-cxl@vger.kernel.org
Subject: Re: [PATCH 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL
Date: Wed, 26 Aug 2026 21:38:10 +0800 [thread overview]
Message-ID: <20260826133812.355470-1-junjie.cao@intel.com> (raw)
In-Reply-To: <20260821081954.1171-5-cp0613@linux.alibaba.com>
Hi Chen Pei,
On Fri, 21 Aug 2026 16:19:54 +0800, Chen Pei wrote:
> tests/data/acpi/riscv64/virt/CEDT.cxl | Bin 0 -> 108 bytes
> tests/data/acpi/riscv64/virt/DSDT.cxl | Bin 0 -> 6212 bytes
> tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++
checkpatch errors on this one: expected files added together with
tests. The flow at the top of bios-tables-test.c wants the new files
added empty and listed in bios-tables-test-allowed-diff.h first, then
the test, then the AML and the emptied allowed-diff in a final patch.
The riscv64 goldens went in that way originally (cc3ba2422554).
Alistair's Acked-by would need re-applying to whichever patch ends up
holding the test code.
Worth settling 3/4 first -- if the _CRS ends up coming from firmware
enumeration, the DSDT here changes anyway.
Many thanks,
Junjie
next prev parent reply other threads:[~2026-08-26 13:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-21 8:19 [PATCH 0/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-08-21 8:19 ` [PATCH 1/4] " Chen Pei
2026-08-21 8:19 ` [PATCH 2/4] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Chen Pei
2026-08-21 8:19 ` [PATCH 3/4] hw/riscv/virt: Provide a 32-bit MMIO window for CXL host bridges Chen Pei
2026-08-26 13:37 ` Junjie Cao
2026-08-27 12:17 ` Chen Pei
2026-08-21 8:19 ` [PATCH 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL Chen Pei
2026-08-26 13:38 ` Junjie Cao [this message]
2026-08-27 12:24 ` Chen Pei
2026-08-21 8:43 ` [PATCH 0/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-08-26 13:37 ` Junjie Cao
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