[PATCH v4 3/6] hw/riscv/virt: Advertise the CXL host bridge to firmware via extra-pci-roots

[Chen Pei <cp0613@linux.alibaba.com>]

The pxb-cxl expander bridge presents as a class 0x0600 host bridge with
a type-0 header, so EDK2's PciBusDxe never recurses into it and never
assigns the CXL root port a memory window or bus numbers.  As a result
build_crs() produces an empty _CRS for the ACPI0016 host bridge and the
CXL devices behind it are not enumerated by the OS.

Advertise the pxb-cxl expander root buses to firmware via the
etc/extra-pci-roots fw_cfg file, the same way arm/virt and x86 do, by
calling pci_bus_add_fw_cfg_extra_pci_roots() from virt_machine_done().
EDK2's PciBusDxe then enumerates behind the CXL host bridge and assigns
the root-port window and bus numbers.  The ACPI tables are rebuilt when
the guest reads them (after that firmware enumeration), so build_crs()
then emits a correct _CRS for the ACPI0016 host bridge.

This approach also scales to multiple pxb-cxl host bridges (each gets
its own window from the shared aperture) and lets firmware size the
window to what is actually behind the bridge, rather than reserving a
fixed carve-out.

Verified by booting an RVA22 guest: the CXL root port and Type3 device
enumerate, and 'cxl enable-memdev' / 'cxl create-region' /
'daxctl online-memory' bring the CXL memory online as system RAM.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---

v4:
- Replaces the v3 QEMU-side firmware simulation with
  pci_bus_add_fw_cfg_extra_pci_roots(), advertising the pxb-cxl
  expander root buses to firmware via etc/extra-pci-roots.  EDK2 then
  enumerates behind the CXL host bridge and assigns the root-port
  window and bus numbers, and build_crs() emits a correct _CRS.  This
  scales to multiple pxb-cxl and lets firmware size the window.

 hw/riscv/virt.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e08c76af4d..67f512cde1 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1237,6 +1237,14 @@ static void virt_machine_done(Notifier *notifier, void *data)
 
     if (s->cxl_devices_state.is_enabled) {
         cxl_fmws_link_targets(&error_fatal);
+
+        /*
+         * Let firmware enumerate the pxb-cxl root buses and assign bus
+         * numbers and windows; build_crs() builds the ACPI0016 _CRS from
+         * the resulting state when the guest reads the ACPI tables.
+         */
+        pci_bus_add_fw_cfg_extra_pci_roots(s->fw_cfg, s->pci_bus,
+                                           &error_abort);
     }
     hwaddr firmware_end_addr;
     vaddr kernel_start_addr;
-- 
2.50.1