Re: [PATCH v20 2/9] PCI: Establish common CXL Port protocol error flow

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] CXL protocol errors on RCD Endpoints bypass the AER-CXL kfifo, leading to dropped correctable errors and UCE race conditions.
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commit 6e514f9fb46669ba2eab05ced2511b382df00bce
Author: Terry Bowman <terry.bowman@amd.com>

PCI: Establish common CXL Port protocol error flow

This commit establishes a single CXL protocol error path shared by Virtual
Hierarchy and Restricted CXL Host topologies. It routes CXL protocol errors,
gated by is_cxl_error(), through an AER-CXL kfifo to a core consumer for
logging and recovery to ensure synchronization.

> diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c
> --- a/drivers/pci/pcie/aer_cxl_rch.c
> +++ b/drivers/pci/pcie/aer_cxl_rch.c
[ ... ]
> -void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
> +bool cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
>  {
> +	struct cxl_rch_error_ctx ctx = { .info = info };
> +
>  	/*
> -	 * Internal errors of an RCEC indicate an AER error in an
> -	 * RCH's downstream port. Check and handle them in the CXL.mem
> -	 * device driver.
> +	 * An RCEC AER internal error indicates an error in an
> +	 * associated RCH Downstream Port or RCD device or both.
> +	 * Forward to the cxl_core module for handling.
>  	 */
>  	if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
>  	    is_aer_internal_error(info))
> -		pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
> +		pcie_walk_rcec(dev, cxl_rch_handle_error_iter, &ctx);
> +
> +	return ctx.enqueued;
>  }

[Severity: High]
Does this check accidentally skip errors logged directly by the RCD itself?

When an RCD detects an error, it logs it in its own AER capability and the
RCEC raises the interrupt. The AER driver's find_source_device() then walks
the RCEC's children, finds the RCD with the set AER status, and calls
handle_error_source() with the RCD device.

Because this condition strictly checks for PCI_EXP_TYPE_RC_EC, it intercepts
errors from the RCEC itself (like RCH Downstream Port errors), but bypasses
handling when the RCD device itself is passed in.

> diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c
> --- a/drivers/pci/pcie/aer_cxl_vh.c
> +++ b/drivers/pci/pcie/aer_cxl_vh.c
[ ... ]
> @@ -54,8 +54,22 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info)
>  	if (!info || !info->is_cxl)
>  		return false;
>  
> -	if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT)
> +	/*
> +	 * RCD (PCI_EXP_TYPE_RC_END) is not included here because RCDs
> +	 * report errors on behalf of upstream RCH Downstream Port and thus
> +	 * require a unique discovery detailed in CXL4.0 spec (12.2.1.1).
> +	 * The RCH device error discovery and RCD forwarding flow begins
> +	 * in cxl_rch_handle_error().
> +	 */
> +	switch (pci_pcie_type(pdev)) {
> +	case PCI_EXP_TYPE_ENDPOINT:
> +	case PCI_EXP_TYPE_ROOT_PORT:
> +	case PCI_EXP_TYPE_UPSTREAM:
> +	case PCI_EXP_TYPE_DOWNSTREAM:
> +		break;
> +	default:
>  		return false;
> +	}
>  
>  	return is_aer_internal_error(info);
>  }

[Severity: High]
Since RCDs are excluded here, does this bypass the AER-CXL kfifo entirely for
RCD protocol errors?

As noted above, cxl_rch_handle_error() skips the RCD device. With the RCD
also falling through to the default case here and returning false, these
errors are never enqueued.

This results in correctable errors being silently dropped without being
traced or cleared (as the legacy cor_error_detected fallback was removed).
For uncorrectable errors, it bypasses the kfifo's synchronization, defeating
the race-condition fix and leaving the system vulnerable to teardown races.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902133933.2992457-1-terry.bowman@amd.com?part=2