Re: [PATCH v3] PCI/AER: Map a raw AER Capability image field by field

[sashiko-bot@kernel.org]

> struct aer_capability_regs is not the hardware layout: the embedded
> struct pcie_tlp_log spans 60 bytes where the Header Log it stands in for
> is 16, so a flat copy misplaces everything behind it.
> 
> extlog_print_pcie(), ghes_handle_aer() and cxl_rch_get_aer_info() work
> around that by stopping at the Header Log, dropping everything past
> offset 44. Flit mode is never decoded either: the Flit bit and Logged
> TLP Size sit at offset 0x18, unread, so the Flit DWORDs at 0x38 are lost
> and the log prints as non-Flit.
> 
> Add aer_cap_regs_unpack() to map the registers individually, taking the
> TLP Log layout from the Flit bit as pcie_read_tlp_log() does. Clamp the
> logged length: Logged TLP Size is 5 bits wide, so an untrusted value
> reaches 31 where dw[] holds 14 and pcie_print_tlp_log() walks
> header_len unbounded.
> [ ... ]
> Reported-by: sashiko-bot@kernel.org
> Closes: https://sashiko.dev/#/patchset/20260904172337.1409775-1-dave.jiang@intel.com?part=5
> Link: https://lore.kernel.org/linux-cxl/CAJZ5v0hDv11cPuztPZsaDd7uwD_49KznJy=tzuRO+dZc=CnAEQ@mail.gmail.com/
> Assisted-by: LLM
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260911164705.841407-1-dave.jiang@intel.com?part=1