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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC3.mail.protection.outlook.com (10.167.23.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.428.7 via Frontend Transport; Wed, 16 Sep 2026 18:46:04 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 16 Sep 2026 11:45:36 -0700 Received: from nvidia-4028GR-scsim.nvidia.com (10.126.231.37) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Wed, 16 Sep 2026 11:45:29 -0700 From: To: , , , , , , , , , , , , , , , CC: , , , , , , , Shameer Kolothum Subject: [PATCH v2 09/10] hw/arm/smmu-common: Allow pxb-cxl as an SMMUv3 primary bus Date: Thu, 17 Sep 2026 00:14:11 +0530 Message-ID: <20260916184412.3825713-10-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260916184412.3825713-1-mhonap@nvidia.com> References: <20260916184412.3825713-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail202.nvidia.com (10.129.68.7) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC3:EE_|CY5PR12MB6323:EE_ X-MS-Office365-Filtering-Correlation-Id: 4cc2d35b-9c4a-4d5e-d4fb-08df1422c357 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|23010399003|82310400026|1800799024|921020|11063799006|56012099006|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SOpz5YnqK5Xi1P5ic7IUwCk+UUhP8oqhQC2iBkMVjsg8Tidj1i6USoG4m+fYzv/kRkzdHs9Y5rUSxytAuxZp1M+YC7F6P5/XdAJTw6Kprl+RXKEwrEm4iBCsh54drcoaxiwrekHq72phH4xG4YRgfLHrCMkpshQOUvwWp08fisSyRxBVN89k1Ej3MEfLVpQyEwwKfJ+tDenD+LZPRZTKR6n2nSKK4wFRb+svPzKmC4g6Nop3xse13sfXilL+BBOgXLnrqXXkqAUtJFHCychSRHkGEW11w5dHUGYBtEj6edUDmAF+is8d8kywhHsm/oIfqB55RlIoxcyhoGP198zqb3lKk+EQcPC34Oqjm/Lo3GG6nCFnIiSmcv8TZGeFXXwPaxVkijGtj7MbV1jH/eH29QwHtXKoM36QVK8EN0/m5Bby1fpxup9uG91ndZxSUktL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2026 18:46:04.7183 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cc2d35b-9c4a-4d5e-d4fb-08df1422c357 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6323 From: Manish Honap The SMMUv3 primary-bus check only accepted pxb-pcie as a valid extra root complex, so a CXL device behind a pxb-cxl could not reach the IOMMU: attaching an arm-smmuv3 to a pxb-cxl bus failed at realize with "SMMU should be attached to a default PCIe root complex (pcie.0) or a pxb-pcie based root complex". A pxb-cxl uses the same PCIe-compatible bus as a pxb-pcie, so accept it too. A CXL Type-2 device passed through with vfio-pci sits behind a pxb-cxl and needs SMMU translation for its DMA and ATS just like a pxb-pcie device. AI-used-for: code (prototype) Signed-off-by: Shameer Kolothum Signed-off-by: Manish Honap --- hw/arm/smmu-common.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 8e40ba603d..42fb098ab2 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -963,19 +963,20 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) s->iommu_ops = &smmu_ops; } /* - * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra - * root complexes to be associated with SMMU. + * We only allow the default PCIe root complex (pcie.0) or pxb-pcie / + * pxb-cxl based extra root complexes to be associated with SMMU. */ if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDGE)) { /* - * This condition matches either the default pcie.0, pxb-pcie, or - * pxb-cxl. For both pxb-pcie and pxb-cxl, parent_dev will be set. - * Currently, we don't allow pxb-cxl as it requires further - * verification. Therefore, make sure this is indeed pxb-pcie. + * pcie.0 has no parent_dev; pxb-pcie and pxb-cxl do. Accept both bus + * types explicitly so other root complexes are still rejected. A + * pxb-cxl uses the same PCIe-compatible bus, so a CXL device behind it + * needs the SMMU just like a pxb-pcie one. */ if (pci_bus->parent_dev) { - if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS)) { + if (!object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_PCIE_BUS) && + !object_dynamic_cast(OBJECT(pci_bus), TYPE_PXB_CXL_BUS)) { goto out_err; } } @@ -990,8 +991,8 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) return; } out_err: - error_setg(errp, "SMMU should be attached to a default PCIe root complex" - "(pcie.0) or a pxb-pcie based root complex"); + error_setg(errp, "SMMU should be attached to a default PCIe root complex " + "(pcie.0), a pxb-pcie, or a pxb-cxl based root complex"); } /* -- 2.25.1