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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: x3RknyRqcQeM7q3zrCvoxafx1v1vxcDWSnKwfLq6wiSJlKRg73yOopnsKo+T1BY1WTppFsham2R2KVl7pjDMhkaCKQttHxEnFWZlMgJkj6nx5KZNN0gIjrKEZRPN+HG2Z+mf3HKSQMYDB0puTtxqlpsJ1AqVw4xn0w88+FUQQXvhATchVCaBR0ELa8lU39r5qSyEE2nqKjp4uWQxeEQuLsepWdU9WON7f4q4HCOg55zKP6OngUK8z6hDyx65jwOs6YuJDrhkcZiWQPzjTv8sYrEbkmafG4u9U+/U7AT/IQajBWQ58+QohVhH1QPtSKq0/h8K2PeE/K2pFj46co3XBdBcDrGVqtMEOpiuYgwRCVRx+BBiw7Zs+ASVMxJX9+szSzvyiygonqFr8b/q78prVqxhw53LdWHekRk1N8jDO16d6AuzTnalVtlMur2Gb80V X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2026 18:45:05.7627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbe102a1-f936-4039-8b12-08df1422a034 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4046 From: Manish Honap Sync the vfio.h additions from the kernel vfio-cxl series: the VFIO_DEVICE_FLAGS_CXL device flag, the CXL Type-2 (0x1e98) HDM memory and component-register sub-types under VFIO_REGION_TYPE_PCI_VENDOR_TYPE, and the component-register geometry capability that reports the BAR and offset of the trapped HDM decoder block. The capability ID is provisional until the kernel series lands, at which point this becomes a scripted linux-headers update. AI-used-for: docs Signed-off-by: Manish Honap --- linux-headers/linux/vfio.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h index c85dcbfe30..c12e55426d 100644 --- a/linux-headers/linux/vfio.h +++ b/linux-headers/linux/vfio.h @@ -215,6 +215,7 @@ struct vfio_device_info { #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) /* vfio-fsl-mc device */ #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) /* Info supports caps */ #define VFIO_DEVICE_FLAGS_CDX (1 << 8) /* vfio-cdx device */ +#define VFIO_DEVICE_FLAGS_CXL (1 << 9) /* vfio-cxl device */ __u32 num_regions; /* Max region index + 1 */ __u32 num_irqs; /* Max IRQ index + 1 */ __u32 cap_offset; /* Offset within info struct of first cap */ @@ -370,6 +371,12 @@ struct vfio_region_info_cap_type { */ #define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) +/* CXL Type-2 device (0x1e98) sub-types for VFIO_REGION_TYPE_PCI_VENDOR_TYPE */ +/* CXL.mem HDM region of a Type-2 device, mmap-able */ +#define VFIO_REGION_SUBTYPE_CXL_MEM (1) +/* CXL HDM decoder registers: read live, guest writes are absorbed */ +#define VFIO_REGION_SUBTYPE_CXL_COMP_REGS (2) + /* sub-types for VFIO_REGION_TYPE_GFX */ #define VFIO_REGION_SUBTYPE_GFX_EDID (1) @@ -497,6 +504,23 @@ struct vfio_region_info_cap_nvlink2_lnkspd { __u32 __pad; }; +/* + * Geometry of a CXL Type-2 device's HDM decoder registers, so a VMM can place + * the trapped component register window where the guest expects it. The trapped + * region spans the whole HDM decoder block (every decoder), not just decoder 0: + * a VMM reads the decoder count and each decoder's committed base from the block + * itself. Additional trapped component capabilities, such as CXL RAS, are + * exposed as their own region subtypes rather than by extending this cap. + */ +#define VFIO_REGION_INFO_CAP_CXL_COMP_REGS 6 + +struct vfio_region_info_cap_cxl_comp_regs { + struct vfio_info_cap_header header; + __u32 bar; + __u32 __resv; + __aligned_u64 offset; +}; + /** * VFIO_DEVICE_GET_IRQ_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 9, * struct vfio_irq_info) -- 2.25.1