From: Jonathan Cameron <jic23@kernel.org>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-perf-users@vger.kernel.org,
will@kernel.org, mark.rutland@arm.com, dave@stgolabs.net,
robin.murphy@arm.com, icheng@nvidia.com
Subject: Re: [RESEND PATCH v4 05/11] perf/cxl: Split the MSI vector out of info->irq
Date: Tue, 22 Sep 2026 02:03:49 +0100 [thread overview]
Message-ID: <20260922020349.213d390c@jic23-hlaptop> (raw)
In-Reply-To: <20260805155911.1304807-6-dave.jiang@intel.com>
On Wed, 5 Aug 2026 08:59:05 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> info->irq means two different things depending on how far probe has got.
> cxl_pmu_parse_caps() sets it to the MSI/MSI-X message number from the CPMU
> Capability register. cxl_pmu_probe() passes that to pci_irq_vector() and
> then overwrites it with the Linux virq, which is what the hotplug callbacks
> hand to irq_set_affinity().
>
> Both are ints called irq, so nothing catches a mix-up, and the valid ranges
> differ. 0 is a fine message number but never a valid virq.
>
> Give the message number its own field. No functional change.
>
> Assisted-by: Claude:claude-opus-4-8
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
next prev parent reply other threads:[~2026-09-22 1:03 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-05 15:59 [RESEND PATCH v4 00/11] perf/cxlpmu: Misc sashiko raised issues fixes Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 01/11] perf/cxl: Program the requested event group on configurable counters Dave Jiang
2026-08-05 16:23 ` sashiko-bot
2026-08-05 15:59 ` [RESEND PATCH v4 02/11] perf/cxl: Clear stale event fields before reprogramming a counter Dave Jiang
2026-08-05 16:12 ` sashiko-bot
2026-09-22 0:58 ` Jonathan Cameron
2026-08-05 15:59 ` [RESEND PATCH v4 03/11] perf/cxl: Fix the counter overflow delta fixup Dave Jiang
2026-09-22 0:59 ` Jonathan Cameron
2026-08-05 15:59 ` [RESEND PATCH v4 04/11] perf/cxl: Accept an overflow interrupt on MSI message number 0 Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 05/11] perf/cxl: Split the MSI vector out of info->irq Dave Jiang
2026-09-22 1:03 ` Jonathan Cameron [this message]
2026-08-05 15:59 ` [RESEND PATCH v4 06/11] cxl/pci: Add the PMUs after configuring events Dave Jiang
2026-08-05 16:51 ` Alison Schofield
2026-09-22 1:05 ` Jonathan Cameron
2026-08-05 15:59 ` [RESEND PATCH v4 07/11] perf/cxl: Don't share the overflow interrupt, and keep it pinned Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 08/11] perf/cxl: Unfreeze counters after handling an overflow interrupt Dave Jiang
2026-08-05 16:15 ` sashiko-bot
2026-08-05 16:35 ` Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 09/11] perf/cxl: Validate the hardware-reported counter width Dave Jiang
2026-08-05 16:16 ` sashiko-bot
2026-08-05 15:59 ` [RESEND PATCH v4 10/11] perf/cxl: Don't log through pmu.dev in the overflow interrupt handler Dave Jiang
2026-08-05 15:59 ` [RESEND PATCH v4 11/11] perf/cxl: Clear stale overflow status before using a counter Dave Jiang
2026-08-05 16:21 ` sashiko-bot
2026-09-22 1:09 ` Jonathan Cameron
2026-09-15 22:43 ` [RESEND PATCH v4 00/11] perf/cxlpmu: Misc sashiko raised issues fixes Ian Rogers
2026-09-18 16:50 ` Dave Jiang
2026-09-22 1:02 ` Jonathan Cameron
2026-10-04 22:09 ` Will Deacon
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