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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by DS2PEPF000061C7.mail.protection.outlook.com (10.167.23.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.8 via Frontend Transport; Wed, 23 Sep 2026 17:33:55 +0000 Received: from ausbcheatha02.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 23 Sep 2026 12:33:53 -0500 From: Ben Cheatham To: , , , , CC: , , , Subject: [PATCH 07/15] cxl/cache: Verify port hierarchy has CXL.cache enabled Date: Wed, 23 Sep 2026 12:33:34 -0500 Message-ID: <20260923173342.5584-8-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923173342.5584-1-Benjamin.Cheatham@amd.com> References: <20260923173342.5584-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C7:EE_|DM6PR12MB4353:EE_ X-MS-Office365-Filtering-Correlation-Id: 089a7f86-2e5d-49ae-53ab-08df1998d7a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|23010399003|376014|1800799024|3023799007|10067099003|18002099003|22082099003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bzyrAgaXwJj3MWPnL1xduV7tXbkrJB9dIG4tgztRHlixeq7mBaaA1zTT/ntbckTwrCrL3RWO4HsBy2ljoP9rIqX2TCrgrWR8U7dh4G3SmHg96FxH5Ag5Wc2HjLsCpOqFFxcK6N3kRBIyOt8ESwTvJqPqiA/WfPsTTo7UscNDaNoaZrTQgQyVeRJKKhAleYREt3YgdAEkSupYgQ4zfaT0v//secnXYX4QF8GqgbTgv2vVeEatLwAsPoRZ8rQn/8eAlZo7ynYuf5ud9GBYvsMRTR4Vox969rYie9JtRKpnN7hiPrWJe6nuoYFyfYyri/8Xo3epH5gG00dRzT2POhLJVeUKgS4dnF+c1YiNBt3VLxJcLvscHOB/MQRo0d9tVzleq3ZuIfsNUReXDfdkohPyRD+O5pcTQ/6/kCzLrqnHADa6Me2uslZUMuGvlFj++g/K X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 17:33:55.3294 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 089a7f86-2e5d-49ae-53ab-08df1998d7a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4353 Check that the ports above a CXL.cache device support CXL.cache and have the protocol enabled. The device's CXL.cache enable bit will be set in a later commit. CXL.cache should be enabled as part of link negotiation by firmware during boot. Upstream ports can't be programmed after boot, but downstream ports can. Reprogramming downstream ports requires a link reset and is may have implications for the underlying PCI device, so fail probe instead of reprogramming the downstream port. Signed-off-by: Ben Cheatham --- drivers/cxl/cache.c | 76 ++++++++++++++++++++++++++++++++++- include/uapi/linux/pci_regs.h | 4 ++ 2 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c index dea5af7b2d3f..dfefd301696a 100644 --- a/drivers/cxl/cache.c +++ b/drivers/cxl/cache.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (C) 2026 Advanced Micro Devices, Inc. */ +#include #include #include "cxlcache.h" @@ -14,6 +15,75 @@ * device-specific driver is required for discovery and portions of set up. */ +static bool cxl_flexbus_cache_enabled(struct device *host) +{ + + u16 dvsec, cap, status; + struct pci_dev *pdev; + int rc; + + if (!dev_is_pci(host)) + return false; + pdev = to_pci_dev(host); + + dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS_PORT); + if (!dvsec) + return false; + + rc = pci_read_config_word(pdev, + dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_CAPABILITY, + &cap); + if (rc) + return false; + + if (!FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_CAP_CACHE, cap)) + return false; + + rc = pci_read_config_word(pdev, + dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS, + &status); + if (rc) + return false; + + return FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, status); +} + +static int cxl_endpoint_cache_enabled(struct cxl_port *endpoint) +{ + struct cxl_dport *dport_iter = endpoint->parent_dport; + struct cxl_port *port_iter = dport_iter->port; + + while (!is_cxl_root(port_iter)) { + /* + * CXL host bridge isn't a PCI device, but we still need to + * check the PCIe root port + */ + if (dev_is_pci(port_iter->uport_dev) && + !cxl_flexbus_cache_enabled(port_iter->uport_dev)) { + dev_dbg(port_iter->uport_dev, + "CXL.cache not supported or enabled\n"); + return -ENXIO; + } + + /* + * Cache can be enabled for dports, but it requires a link + * reset. Could be done here, but should probably be done + * by the endpoint's driver. + */ + if (!cxl_flexbus_cache_enabled(dport_iter->dport_dev)) { + dev_dbg(dport_iter->dport_dev, + "CXL.cache not supported or enabled\n"); + return -ENXIO; + } + + dport_iter = port_iter->parent_dport; + port_iter = dport_iter->port; + } + + return 0; +} + /** * devm_cxl_add_cachedev - Add a CXL cache device * @cxlds: CXL device state to associate with the cachedev @@ -71,7 +141,11 @@ static int cxl_cache_probe(struct device *dev) return rc; } - return 0; + rc = cxl_endpoint_cache_enabled(cxlcd->endpoint); + if (rc) + dev_err(dev, "CXL.cache not enabled on parent port(s)"); + + return rc; } static struct cxl_driver cxl_cache_driver = { diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 5383b54ede96..9146ee574de8 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1392,6 +1392,10 @@ /* CXL r4.0, 8.1.8: Flex Bus DVSEC */ #define PCI_DVSEC_CXL_FLEXBUS_PORT 7 +#define PCI_DVSEC_CXL_FLEXBUS_PORT_CAPABILITY 0xA +#define PCI_DVSEC_CXL_FLEXBUS_PORT_CAP_CACHE _BITUL(0) +#define PCI_DVSEC_CXL_FLEXBUS_PORT_CONTROL 0xC +#define PCI_DVSEC_CXL_FLEXBUS_PORT_CTRL_CACHE_EN _BITUL(0) #define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS 0xE #define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE _BITUL(0) #define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM _BITUL(2) -- 2.53.0