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Thu, 1 Oct 2026 07:01:22 -0500 From: To: , CC: , , , , , , , Alejandro Lucero Subject: [PATCH v2 4/4] sfc: add multipf support Date: Thu, 1 Oct 2026 14:20:23 +0100 Message-ID: <20261001132023.17032-5-alucerop@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261001132023.17032-1-alucerop@amd.com> References: <20261001132023.17032-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002316:EE_|SAVPR12MB999144:EE_ X-MS-Office365-Filtering-Correlation-Id: 53893a32-9ee8-4ad4-74b2-08df1fb3cc93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|23010399003|6133799003|22082099003|18002099003|10067099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: YFtqJWxtAYYr7nRe5968yYKOCAUHaFXgtbDHqQ9eJC3uMmzBBo4QOiwIPAWhrvEMQD91oZCE1I49oUxcpEz2Bh0BjT3UY8Q4ZyCA3F30bP2124v4tYD/qw6DGsKPsDu6p2NcJDmLZu9BowdAli0GwuZ2ddZzBdXkiKJX01OcEBBQZiAr2/1cqjdhLF1/QFVHFq26l7yEG05Fe5zbfCUiwKz3x1h7O6ZZKz9YxEbFqx4IEUY2474Sqqc0aqgb8L8fR0Dp2a/1Tr777Cjk4jphfSqmqj++hby4qTpHsgOy+lfryHH85ropzyJ8N/j7T9KTCfuAJB4i2/xvK2Ij9KI05DAD4XUKXqUe132S6BlaRV0sBpBRh3HkqAzbw0XRLEzMtCHNpBa9gOc/A4z1M7lIjRdpWP6ttUxkDKTyP+yUUzPdFv2XkPJ/S65qnizH43g++IxAWEzQSP1MViSbHA7cvhQGoExFyLNzTZF9NjmkwKevP0/hvcVGJ+0ydyg37R04gI54PWt1vTHcmHB030uM18PgRn1axmOmJFQBnAg1YXi8Jq0yBK4WNRaqdXe2NMJv0AwkTazCJOiqTfr1sh4WRydg0pXvNslgjqfvhCwh4f7GhjLIztl8i35AI7jiHAxDGkgo2P3K6HvhH1YNT5adE6MJp7pVOFAIRmwuNWKs9sZ87j60YmJKdqVv7CzHeCwbIFPVNHMtvhTKvZ0YsH6/Uw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700016)(23010399003)(6133799003)(22082099003)(18002099003)(10067099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: E6Mxb6iecH7q1zdkNC1hpiLi4fqWNc8LznPxAExKaxpIgvjN/f0wtcfO5R8sIbkFhZW5nM8supXRsdLIYelpN5Xh6jxWxKwB8Q6gZdSVRlazU02gUTiHeuYVd9tUgnnxVjTGimuIUxMannnA5RxdLHKlcgyB6ov+Zx0icTcFHyj5HhQW+IsjiGSPiAl+NNB6F7paAz/8fQ4MEdXybay0jBm9cUIW+D2ncCihqRfheBcVxWqrCwOygDznSTa/2Eky6NWu07JuI0G0HnrnTmU0RCJGSR5MpVtJYjqvqL6a9tyJMutNRe+iysDk1xlOJ+bpKxccVeUpM7vJK7Av1hWGhwtdo6eG1D95y7Po0FQ282qfDIyppsPIT9pIXgvN6dYpHYHvBC9+IL304NbN8HeG1Pof+o7i90vBmcyR9GPZe/QJUEthPbHX7A2pgwQBCjiX X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2026 12:02:00.0639 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53893a32-9ee8-4ad4-74b2-08df1fb3cc93 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002316.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAVPR12MB999144 From: Alejandro Lucero Use CXL core accelerator API for linking a non-PF0 PF to the CXL region its related PF0 CXL memdev is attached to, allowing non-PF0 PF release if such a CXL region is released itself. This can occur in different scenarios like PF0 release or CXL memdev release. Obtain the CXL HPA region to work with and the ioremap based on such HPA and an offset based on the PF index. Refactor CXL initialization with different code paths for PF0 and non PF0 PFs. Signed-off-by: Alejandro Lucero --- drivers/net/ethernet/sfc/efx_cxl.c | 100 ++++++++++++++++++++++++++--- 1 file changed, 91 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 348d7404cd7a..f884580cb528 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -13,8 +13,69 @@ #include "efx_cxl.h" #define EFX_CTPIO_BUFFER_SIZE SZ_256M +#define EFX_CTPIO_BUFFER_PER_PF_SIZE SZ_8M -int efx_cxl_init(struct efx_probe_data *probe_data) +static int cxl_map(struct efx_probe_data *probe_data, struct efx_cxl *cxl, + u64 devfn, struct range cxl_pio_range) +{ + struct efx_nic *efx = &probe_data->efx; + struct pci_dev *pci_dev = efx->pci_dev; + u64 cxl_pio_pf_start; + + cxl_pio_pf_start = cxl_pio_range.start + + devfn * EFX_CTPIO_BUFFER_PER_PF_SIZE; + + cxl->ctpio_cxl = ioremap_wc(cxl_pio_pf_start, + EFX_CTPIO_BUFFER_PER_PF_SIZE); + if (!cxl->ctpio_cxl) { + pci_err(pci_dev, "CXL ioremap region (%pra) failed\n", + &cxl_pio_range); + return -ENOMEM; + } + return 0; +} + +static int efx_cxl_non_pf0_init(struct efx_probe_data *probe_data) +{ + struct efx_nic *efx = &probe_data->efx; + struct pci_dev *pci_dev = efx->pci_dev; + struct range cxl_pio_range; + struct efx_cxl *cxl; + u64 devfn; + + devfn = PCI_FUNC(pci_dev->devfn); + + struct pci_dev *pf0_pci_dev __free(pci_dev_put) = + pci_get_slot(pci_dev->bus, PCI_DEVFN(PCI_SLOT(devfn), 0)); + + /* This should not happen! */ + if (!pf0_pci_dev) + return 0; + + /* Is the PF0 device configured with and using CXL? */ + if (!pcie_is_cxl(pf0_pci_dev)) + return 0; + + if (!cxl_get_range_and_link(&pf0_pci_dev->dev, &pci_dev->dev, + &cxl_pio_range)) + return -EPROBE_DEFER; + + cxl = kzalloc_obj(*cxl, GFP_KERNEL); + if (!cxl) + return -ENOMEM; + + if (cxl_map(probe_data, cxl, (u64)devfn, cxl_pio_range)) { + kfree(cxl); + return -ENOMEM; + } + + probe_data->cxl = cxl; + probe_data->cxl_pio_initialised = true; + + return 0; +} + +static int efx_cxl_pf0_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; struct pci_dev *pci_dev = efx->pci_dev; @@ -80,26 +141,47 @@ int efx_cxl_init(struct efx_probe_data *probe_data) return PTR_ERR(cxl->cxlmd); } - cxl->ctpio_cxl = ioremap_wc(cxl_pio_range.start, - range_len(&cxl_pio_range)); - if (!cxl->ctpio_cxl) { - pci_err(pci_dev, "CXL ioremap region (%pra) failed\n", - &cxl_pio_range); + if (cxl_map(probe_data, cxl, 0, cxl_pio_range)) return -ENOMEM; - } - probe_data->cxl_pio_initialised = true; probe_data->cxl = cxl; - + probe_data->cxl_pio_initialised = true; return 0; } +int efx_cxl_init(struct efx_probe_data *probe_data) +{ + struct efx_nic *efx = &probe_data->efx; + struct pci_dev *pci_dev = efx->pci_dev; + u8 devfn; + + if (efx->type->is_vf) + return 0; + + /* are we PF0? */ + devfn = PCI_FUNC(pci_dev->devfn); + if (devfn == 0) + return efx_cxl_pf0_init(probe_data); + else + return efx_cxl_non_pf0_init(probe_data); +} + void efx_cxl_exit(struct efx_probe_data *probe_data) { + struct efx_nic *efx = &probe_data->efx; + struct pci_dev *pci_dev = efx->pci_dev; + u8 devfn; + if (!probe_data->cxl) return; iounmap(probe_data->cxl->ctpio_cxl); + + devfn = PCI_FUNC(pci_dev->devfn); + if (devfn == 0) + return; + + kfree(probe_data->cxl); } MODULE_IMPORT_NS("CXL"); -- 2.34.1