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De Francesco" To: linux-cxl@vger.kernel.org, Dave Jiang Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com Subject: Re: [PATCH v2 2/3] cxl/test: Add cxl_test CFMWS support for extended linear cache Date: Mon, 17 Nov 2025 16:34:00 +0100 Message-ID: <2049680.vYEEZNnvjD@fdefranc-mobl3> In-Reply-To: <20251117144611.903692-3-dave.jiang@intel.com> References: <20251117144611.903692-1-dave.jiang@intel.com> <20251117144611.903692-3-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Monday, November 17, 2025 3:46:10=E2=80=AFPM Central European Standard T= ime Dave Jiang wrote: > Add a module parameter to allow activation of extended linear cache > on the auto region for cxl_test. The current platform implementation > for extended linear cache is 1:1 of DRAM and CXL memory. A CFMWS is > created with the size of both memory together where DRAM takes the > first part of the memory range and CXL covers the second part. The > current CXL auto region on cxl_test consists of 2 256M devices that > creates a 512M region. The new extended linear cache setup will have > 512M DRAM and 512M CXL memory for a total of 1G CFMWS. The hardware > decoders must have their starting offset moved to after the DRAM region > to handle the CXL regions. >=20 > Reviewed-by: Jonathan Cameron > Signed-off-by: Dave Jiang > --- > v2: > - change to use mock_auto_region_size > --- Reviewed-by: Fabio M. De Francesco > tools/testing/cxl/test/cxl.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) >=20 > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c > index f0e734536081..2c3979c0b505 100644 > --- a/tools/testing/cxl/test/cxl.c > +++ b/tools/testing/cxl/test/cxl.c > @@ -15,6 +15,7 @@ > #include "mock.h" > =20 > static int interleave_arithmetic; > +static bool extended_linear_cache; > =20 > #define FAKE_QTG_ID 42 > =20 > @@ -429,6 +430,24 @@ static struct cxl_mock_res *alloc_mock_res(resource_= size_t size, int align) > return res; > } > =20 > +/* > + * Only update CFMWS0 as this is used by the auto region. > + */ > +static void cfmws_elc_update(struct acpi_cedt_cfmws *window, int index) > +{ > + if (!extended_linear_cache) > + return; > + > + if (index !=3D 0) > + return; > + > + /* > + * The window size should be 2x of the CXL region size where half is > + * DRAM and half is CXL > + */ > + window->window_size =3D mock_auto_region_size * 2; > +} > + > static int populate_cedt(void) > { > struct cxl_mock_res *res; > @@ -453,6 +472,7 @@ static int populate_cedt(void) > for (i =3D cfmws_start; i <=3D cfmws_end; i++) { > struct acpi_cedt_cfmws *window =3D mock_cfmws[i]; > =20 > + cfmws_elc_update(window, i); > res =3D alloc_mock_res(window->window_size, SZ_256M); > if (!res) > return -ENOMEM; > @@ -783,6 +803,8 @@ static void mock_init_hdm_decoder(struct cxl_decoder = *cxld) > } > =20 > base =3D window->base_hpa; > + if (extended_linear_cache) > + base +=3D mock_auto_region_size; > cxld->hpa_range =3D (struct range) { > .start =3D base, > .end =3D base + mock_auto_region_size - 1, > @@ -1609,6 +1631,8 @@ static __exit void cxl_test_exit(void) > =20 > module_param(interleave_arithmetic, int, 0444); > MODULE_PARM_DESC(interleave_arithmetic, "Modulo:0, XOR:1"); > +module_param(extended_linear_cache, bool, 0444); > +MODULE_PARM_DESC(extended_linear_cache, "Enable extended linear cache su= pport"); > module_init(cxl_test_init); > module_exit(cxl_test_exit); > MODULE_LICENSE("GPL v2"); > --=20 > 2.51.1 >=20 >=20 >=20