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Wed, 4 Nov 2026 11:38:03 +0000 (GMT) Received: from epcpadp2new (unknown [182.195.40.142]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4jKNjR5dkkz2SSKX; Wed, 4 Nov 2026 11:38:03 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20261104113014epcas5p1dbf4b09e2849d28b46eb39db7990a54f~k1Ca--Rd50210802108epcas5p1A; Wed, 4 Nov 2026 11:30:14 +0000 (GMT) Received: from unvme-SYS-221H-TN24R.samsungds.net (unknown [107.99.40.127]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20261104113012epsmtip1ca93aed51b3be29c21f0b709647aa5c8~k1CYtrxjj2364123641epsmtip1L; Wed, 4 Nov 2026 11:30:11 +0000 (GMT) From: Shrihari E S To: jic23@kernel.org, junjie.cao@linux.dev, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, anisa.su887@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com Cc: shrihari.s@samsung.com, arun.george@samsung.com, cpgs@samsung.com, dave@stgolabs.net, dongjoo.seo1@samsung.com, gost.dev@samsung.com, s.neeraj@samsung.com, vikash.k5@samsung.com, anisa.su@samsung.com, junjie.cao@intel.com Subject: [PATCH qemu v1 1/8] hw/pci: Refactor flitmode from PCIESlot to PCIEPort Date: Wed, 4 Nov 2026 17:22:35 +0530 Message-Id: <282821294.121793792283779.JavaMail.epsvc@epcpadp2new> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261104115242.2035807-1-shrihari.s@samsung.com> X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20261104113014epcas5p1dbf4b09e2849d28b46eb39db7990a54f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CPGSPASS: Y X-Hop-Count: 3 X-CMS-RootMailID: 20261104113014epcas5p1dbf4b09e2849d28b46eb39db7990a54f References: <20261104115242.2035807-1-shrihari.s@samsung.com> Move the 'flitmode' field from PCIESlot to its parent PCIEPort so that all the derived port types carry the 256-byte flit mode state in a single field. The 'x-256b-flit' property defaults to off on all the port types. The x-256b-flit property is based on a patch series from Davidlohr Bueso that adds flit mode signaling for CXL ports[1]. [1]: https://lore.kernel.org/all/20251103195209.1319917-2-dave@stgolabs.net/ Signed-off-by: Shrihari E S --- hw/pci-bridge/cxl_downstream.c | 6 +++--- hw/pci-bridge/cxl_root_port.c | 6 +++--- hw/pci-bridge/cxl_upstream.c | 11 +++++++---- hw/pci/pcie.c | 2 +- include/hw/pci-bridge/cxl_upstream_port.h | 1 - include/hw/pci/pcie_port.h | 2 +- 6 files changed, 15 insertions(+), 13 deletions(-) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index d1e27994a3..134b91220a 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -118,7 +118,7 @@ static void cxl_dsp_reset(DeviceState *qdev) static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s = PCIE_SLOT(d); + PCIEPort *p = PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -132,7 +132,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ .cap = 0x27, /* Cache, IO, Mem, non-MLD */ .ctrl = 0x02, /* IO always enabled */ - .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ + .status = p->flitmode ? 0x6 : 0x26, /* lack of 68B */ .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ }; cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, @@ -259,7 +259,7 @@ static const Property cxl_dsp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), }; static void cxl_dsp_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 0ee18ef5c3..01463dbb07 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -112,7 +112,7 @@ static void latch_registers(CXLRootPort *crp) static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s = PCIE_SLOT(d); + PCIEPort *p = PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -135,7 +135,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ .cap = 0x26, /* IO, Mem, non-MLD */ .ctrl = 0x2, - .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ + .status = p->flitmode ? 0x6 : 0x26, /* lack of 68B */ .rcvd_mod_ts_data_phase1 = 0xef, }; cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, @@ -237,7 +237,7 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), }; static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index ef5480b116..0b1fa9594b 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -136,7 +136,8 @@ static void latch_registers(CXLUpstreamPort *usp) uint32_t *write_msk = usp->cxl_cstate.crb.cache_mem_regs_write_mask; cxl_component_register_init_common(reg_state, write_msk, - CXL2_UPSTREAM_PORT, usp->flitmode); + CXL2_UPSTREAM_PORT, + PCIE_PORT(usp)->flitmode); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8); } @@ -147,7 +148,8 @@ static void cxl_usp_reset(DeviceState *qdev) pci_bridge_reset(qdev); pcie_cap_deverr_reset(d); - pcie_cap_fill_link_ep_usp(d, usp->width, usp->speed, usp->flitmode); + pcie_cap_fill_link_ep_usp(d, usp->width, usp->speed, + PCIE_PORT(usp)->flitmode); latch_registers(usp); } @@ -168,7 +170,8 @@ static void build_dvsecs(CXLUpstreamPort *usp) dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ .cap = 0x27, /* Cache, IO, Mem, non-MLD */ .ctrl = 0x27, /* Cache, IO, Mem */ - .status = usp->flitmode ? 0x6 : 0x26, /* lack of 68B */ + .status = PCIE_PORT(usp)->flitmode ? + 0x6 : 0x26, /* lack of 68B */ .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ }; cxl_component_create_dvsec(cxl_cstate, CXL2_UPSTREAM_PORT, @@ -436,7 +439,7 @@ static const Property cxl_upstream_props[] = { speed, PCIE_LINK_SPEED_32), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_BOOL("x-256b-flit", CXLUpstreamPort, flitmode, false), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), }; static void cxl_upstream_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1de0b1e4fd..4f6fc9db61 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -217,7 +217,7 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ } - pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->flitmode); + pcie_cap_fill_lnk(exp_cap, s->width, s->speed, PCIE_PORT(s)->flitmode); } int pcie_cap_init(PCIDevice *dev, uint8_t offset, diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h index d4186234c8..e8f5e43faf 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -21,7 +21,6 @@ typedef struct CXLUpstreamPort { PCIExpLinkSpeed speed; PCIExpLinkWidth width; - bool flitmode; DOECap doe_cdat; uint64_t sn; diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 53cd64c5ed..1bcc734649 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -33,6 +33,7 @@ struct PCIEPort { /*< private >*/ PCIBridge parent_obj; /*< public >*/ + bool flitmode; /* pci express switch port */ uint8_t port; @@ -58,7 +59,6 @@ struct PCIESlot { PCIExpLinkSpeed speed; PCIExpLinkWidth width; - bool flitmode; /* Disable ACS (really for a pcie_root_port) */ bool disable_acs; -- 2.34.1