From: Dave Jiang <dave.jiang@intel.com>
To: Richard Cheng <icheng@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-perf-users@vger.kernel.org,
jic23@kernel.org, will@kernel.org, mark.rutland@arm.com,
dave@stgolabs.net, robin.murphy@arm.com, sashiko-bot@kernel.org,
Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Subject: Re: [PATCH v3 5/9] perf/cxl: Accept an overflow interrupt on MSI message number 0
Date: Mon, 3 Aug 2026 07:30:00 -0700 [thread overview]
Message-ID: <2d89c314-c0d9-4895-83cf-52f12a3f6ef0@intel.com> (raw)
In-Reply-To: <anAs42gO1Yd7MCid@MWDK4CY14F>
On 8/2/26 10:57 PM, Richard Cheng wrote:
> On Fri, Jul 31, 2026 at 04:28:23PM +0800, Dave Jiang wrote:
>> cxl_pmu_probe() rejects the PMU when info->msi_vec <= 0, but that field
>> holds the MSI/MSI-X message number the device signals overflow on. The
>> field is 0-based, and -1 means no interrupt support. Message number 0 is
>> valid and pci_irq_vector() takes a 0-based index, so a compliant device
>> signalling on the first vector fails to probe.
>>
>> Reject only the no-interrupt case, matching how the CXL mailbox and event
>> interrupts handle it.
>>
>> Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
>> Reported-by: sashiko-bot@kernel.org
>> Closes: https://sashiko.dev/#/patchset/20260715191454.459673-1-dave@stgolabs.net?part=1
>> Assisted-by: Claude:claude-opus-4-8
>> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
>> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> v3:
>> - Rebase on the preceding patch, so this tests info->msi_vec rather than
>> info->irq. The fix is unchanged and the hunk is still one line.
>> - Not guarding against pci_irq_vector()'s INTx fallback for vector 0, which
>> it returns when neither MSI nor MSI-X is enabled. A v3 draft added a
>> pci_dev_msi_enabled() check for that, but a modern CXL device wiring up
>> INTx is not a realistic prospect, and the consequence otherwise is a PMU
>> that counts nothing rather than anything unsafe. Left alone to keep this
>> a one-liner.
>> ---
>> drivers/perf/cxl_pmu.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
>> index 56e6ae7bebf7..c9e30cb149df 100644
>> --- a/drivers/perf/cxl_pmu.c
>> +++ b/drivers/perf/cxl_pmu.c
>> @@ -875,7 +875,7 @@ static int cxl_pmu_probe(struct device *dev)
>> .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
>> };
>>
>> - if (info->msi_vec <= 0)
>> + if (info->msi_vec < 0)
>> return -EINVAL;
>>
>
> Hi Dave,
>
> I agree that 0 is a legal message number, but do we need to check whether
> MSI is actually enabled ?
I actually dropped the check and added notes so sashiko doesn't freak out. I don't think it's necessary given there's not likely to have devices with INTX support.
>
> something like
> """
> if (info->msi_vec < 0 || (!pdev->msi_enabled && !pdev->msix_enabled))
> return -EINVAL;
> """
I can add that if you still think it's needed. The one thing I can think of is someone pass in no_msi at the kernel commandline.
>
> Best regards,
> Richard Cheng
>
>
>
>
>> rc = pci_irq_vector(pdev, info->msi_vec);
>> --
>> 2.55.0
>>
>>
next prev parent reply other threads:[~2026-08-03 14:30 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-31 23:28 [PATCH v3 0/9] perf/cxlpmu: Misc sashiko raised issues fixes Dave Jiang
2026-07-31 23:28 ` [PATCH v3 1/9] perf/cxl: Program the requested event group on configurable counters Dave Jiang
2026-07-31 23:38 ` sashiko-bot
2026-07-31 23:28 ` [PATCH v3 2/9] perf/cxl: Clear stale event fields before reprogramming a counter Dave Jiang
2026-07-31 23:40 ` sashiko-bot
2026-07-31 23:28 ` [PATCH v3 3/9] perf/cxl: Fix the counter overflow delta fixup Dave Jiang
2026-07-31 23:37 ` sashiko-bot
2026-07-31 23:28 ` [PATCH v3 4/9] perf/cxl: Split the MSI vector out of info->irq Dave Jiang
2026-07-31 23:45 ` sashiko-bot
2026-08-03 12:04 ` Robin Murphy
2026-08-03 16:01 ` Dave Jiang
2026-07-31 23:28 ` [PATCH v3 5/9] perf/cxl: Accept an overflow interrupt on MSI message number 0 Dave Jiang
2026-08-03 5:57 ` Richard Cheng
2026-08-03 14:30 ` Dave Jiang [this message]
2026-08-03 14:40 ` Richard Cheng
2026-07-31 23:28 ` [PATCH v3 6/9] perf/cxl: Don't share the overflow interrupt, and keep it pinned Dave Jiang
2026-07-31 23:50 ` sashiko-bot
2026-07-31 23:28 ` [PATCH v3 7/9] perf/cxl: Unfreeze counters after handling an overflow interrupt Dave Jiang
2026-07-31 23:40 ` sashiko-bot
2026-08-03 4:00 ` Richard Cheng
2026-08-03 11:26 ` Robin Murphy
2026-07-31 23:28 ` [PATCH v3 8/9] perf/cxl: Validate the hardware-reported counter width Dave Jiang
2026-07-31 23:28 ` [PATCH v3 9/9] perf/cxl: Don't log through pmu.dev in the overflow interrupt handler Dave Jiang
2026-07-31 23:46 ` sashiko-bot
2026-08-03 5:29 ` Richard Cheng
2026-08-03 16:39 ` Dave Jiang
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