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X-CSE-ConnectionGUID: 2B6K4EepT4uKfQYp528D4A== X-CSE-MsgGUID: irVPnTWEQFu5USgMJvBfbQ== X-IronPort-AV: E=McAfee;i="6700,10204,11427"; a="52176489" X-IronPort-AV: E=Sophos;i="6.15,272,1739865600"; d="scan'208";a="52176489" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2025 10:20:46 -0700 X-CSE-ConnectionGUID: 60sHhrFoTzSEyv3EMg0+nA== X-CSE-MsgGUID: y0+hh25nS+u0BwZIYlvMRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,272,1739865600"; d="scan'208";a="141481385" Received: from vverma7-desk1.amr.corp.intel.com (HELO [10.125.108.128]) ([10.125.108.128]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2025 10:20:45 -0700 Message-ID: <2f7ec84e-9df0-4753-97d2-91e6ee773091@intel.com> Date: Thu, 8 May 2025 10:20:44 -0700 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v14 03/22] cxl: move pci generic code To: Alejandro Lucero Palau , Alison Schofield , alejandro.lucero-palau@amd.com Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org, dan.j.williams@intel.com, edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com, Ben Cheatham , Fan Ni , Jonathan Cameron References: <20250417212926.1343268-1-alejandro.lucero-palau@amd.com> <20250417212926.1343268-4-alejandro.lucero-palau@amd.com> <92ff6f90-3b32-490e-9b62-0f516cb89ef4@amd.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <92ff6f90-3b32-490e-9b62-0f516cb89ef4@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 5/8/25 5:45 AM, Alejandro Lucero Palau wrote: > > On 5/8/25 01:36, Alison Schofield wrote: >> On Thu, Apr 17, 2025 at 10:29:06PM +0100, alejandro.lucero-palau@amd.com wrote: >>> From: Alejandro Lucero >>> >>> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization >>> meanwhile cxl/pci.c implements the functionality for a Type3 device >>> initialization. >>> >>> Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be >>> exported and shared with CXL Type2 device initialization. >>> >>> Signed-off-by: Alejandro Lucero >>> Reviewed-by: Dave Jiang >>> Reviewed-by: Ben Cheatham >>> Reviewed-by: Fan Ni >>> Reviewed-by: Jonathan Cameron >>> --- >>>   drivers/cxl/core/core.h       |  2 + >>>   drivers/cxl/core/pci.c        | 62 +++++++++++++++++++++++++++++++ >>>   drivers/cxl/core/regs.c       |  1 - >>>   drivers/cxl/cxl.h             |  2 - >>>   drivers/cxl/cxlpci.h          |  2 + >>>   drivers/cxl/pci.c             | 70 ----------------------------------- >>>   include/cxl/pci.h             | 13 +++++++ >>>   tools/testing/cxl/Kbuild      |  1 - >>>   tools/testing/cxl/test/mock.c | 17 --------- >> The commit log doesn't mention these cxl/test changes. >> Why are these done? > > > If I recall this right, moving the code has the effect of not requiring this code anymore. > > > This comes from Dan's work for fixing the problem with that code moving. I think what Alison is hinting at is to add a blurb in the commit log for the purpose of the cxl_test changes so a patch reader later on will have context of those changes. DJ > > >> >>> index af2594e4f35d..3c6a071fbbe3 100644 >>> --- a/tools/testing/cxl/test/mock.c >>> +++ b/tools/testing/cxl/test/mock.c >>> @@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, >>>   } >>>   EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); >>>   -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev, >>> -                          struct cxl_dport *dport) >>> -{ >>> -    int index; >>> -    resource_size_t component_reg_phys; >>> -    struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); >>> - >>> -    if (ops && ops->is_mock_port(dev)) >>> -        component_reg_phys = CXL_RESOURCE_NONE; >>> -    else >>> -        component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); >>> -    put_cxl_mock_ops(index); >>> - >>> -    return component_reg_phys; >>> -} >>> -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL"); >>> - >>>   void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) >>>   { >>>       int index; >>> --  >>> 2.34.1 >>> >>>