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Wed, 4 Nov 2026 11:38:03 +0000 (GMT) Received: from epcpadp2new (unknown [182.195.40.142]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4jKNjR6lKzz6B9m5; Wed, 4 Nov 2026 11:38:03 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20261104113044epcas5p2f8aa4ebe7305b60819571c1a8aefe295~k1C3UXcY22350023500epcas5p2I; Wed, 4 Nov 2026 11:30:44 +0000 (GMT) Received: from unvme-SYS-221H-TN24R.samsungds.net (unknown [107.99.40.127]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20261104113041epsmtip1e29814f825c506ece958cb88d08f6ee8~k1C0KytrG2364123641epsmtip1c; Wed, 4 Nov 2026 11:30:41 +0000 (GMT) From: Shrihari E S To: jic23@kernel.org, junjie.cao@linux.dev, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, anisa.su887@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com Cc: shrihari.s@samsung.com, arun.george@samsung.com, cpgs@samsung.com, dave@stgolabs.net, dongjoo.seo1@samsung.com, gost.dev@samsung.com, s.neeraj@samsung.com, vikash.k5@samsung.com, anisa.su@samsung.com, junjie.cao@intel.com Subject: [PATCH qemu v1 7/8] hw/cxl: Wire SVC and Dev3 capabilities to CXL Type 3 device Date: Wed, 4 Nov 2026 17:22:41 +0530 Message-Id: <331418503.141793792283935.JavaMail.epsvc@epcpadp2new> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261104115242.2035807-1-shrihari.s@samsung.com> X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20261104113044epcas5p2f8aa4ebe7305b60819571c1a8aefe295 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CPGSPASS: Y X-Hop-Count: 3 X-CMS-RootMailID: 20261104113044epcas5p2f8aa4ebe7305b60819571c1a8aefe295 References: <20261104115242.2035807-1-shrihari.s@samsung.com> Add the SVC and Dev3 capabilities to the CXL type 3 device to make it work as a UIO completer. The x-uio option works together with the x-svc and x-256b-flit options: the device carries the UIO capability when all three are set, and logs a warning that UIO is not enabled when x-uio is set without x-svc and x-256b-flit. Signed-off-by: Shrihari E S Signed-off-by: Dongjoo Seo --- hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 1 + 2 files changed, 30 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 778a18ddea..12430c77d2 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -17,6 +17,7 @@ #include "hw/mem/memory-device.h" #include "hw/mem/pc-dimm.h" #include "hw/pci/pci.h" +#include "hw/pci/pcie_dev3.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-properties-system.h" #include "qapi/error.h" @@ -1191,6 +1192,33 @@ void ct3_realize(PCIDevice *pci_dev, Error **errp) pcie_doe_init(pci_dev, &ct3d->doe_comp, 0x1b0, doe_comp_prot, true, CXL_T3_MSIX_PCIE_DOE_COMPLIANCE); + /* + * The HDM decoder UIO capability builds on the SVC and 256-byte + * flit mode capabilities in the PCIe config space: the device + * carries the UIO capability when it is configured for SVC and + * 256-byte flit mode as well. + */ + if (ct3d->uio_comp_capable && (!ct3d->svc || !ct3d->flitmode)) { + warn_report("x-uio=on requires x-svc=on and x-256b-flit=on; " + "UIO will not be enabled on this device"); + ct3d->uio_comp_capable = false; + } + + if (ct3d->svc) { + /* SVC capability of the type3 device */ + rc = pcie_svc_cap_init(pci_dev, 0x200 + PCI_ERR_SIZEOF, + ct3d->flitmode, errp); + if ((rc >= 0) && ct3d->uio_comp_capable) { + /* + * The Dev3 Capability is placed after SVC in the PCIe + * config space, and the device is initialized as a UIO + * completer. + */ + pcie_dev3_cap_init(pci_dev, 0x200 + PCI_ERR_SIZEOF + PCI_SVC_SIZEOF, + false, true, errp); + } + } + /* Set default value for patrol scrub attributes */ ct3d->patrol_scrub_attrs.scrub_cycle_cap = CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT | @@ -1556,6 +1584,7 @@ static const Property ct3_props[] = { width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", CXLType3Dev, flitmode, false), DEFINE_PROP_BOOL("hdm-db", CXLType3Dev, hdmdb, false), + DEFINE_PROP_BOOL("x-svc", CXLType3Dev, svc, false), DEFINE_PROP_BOOL("x-uio", CXLType3Dev, uio_comp_capable, false), DEFINE_PROP_UINT16("chmu-port", CXLType3Dev, cxl_dstate.chmu[0].port, 0), }; diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index e8480026c3..a095febf90 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -884,6 +884,7 @@ struct CXLType3Dev { PCIExpLinkWidth width; bool flitmode; bool uio_comp_capable; + bool svc; /* DOE */ DOECap doe_cdat; -- 2.34.1