From: "Bowman, Terry" <terry.bowman@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
dave@stgolabs.net, dave.jiang@intel.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
dan.j.williams@intel.com, bhelgaas@google.com,
mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com,
Benjamin.Cheatham@amd.com, rrichter@amd.com,
nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com,
lukas@wunner.de, ming.li@zohomail.com,
PradeepVineshReddy.Kodamati@amd.com
Subject: Re: [PATCH v8 16/16] CXL/PCI: Disable CXL protocol errors during CXL Port cleanup
Date: Thu, 24 Apr 2025 11:37:03 -0500 [thread overview]
Message-ID: <37b14a9f-8520-46f9-98a9-8e3fa8e15e8d@amd.com> (raw)
In-Reply-To: <20250417111309.00000672@huawei.com>
On 4/17/2025 5:13 AM, Jonathan Cameron wrote:
> Hi Terry,
>
>>>> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
>>>> index d3068f5cc767..d1ef0c676ff8 100644
>>>> --- a/drivers/pci/pcie/aer.c
>>>> +++ b/drivers/pci/pcie/aer.c
>>>> @@ -977,6 +977,31 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)
>>>> }
>>>> EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL");
>>>>
>>>> +/**
>>>> + * pci_aer_mask_internal_errors - mask internal errors
>>>> + * @dev: pointer to the pcie_dev data structure
>>>> + *
>>>> + * Masks internal errors in the Uncorrectable and Correctable Error
>>>> + * Mask registers.
>>>> + *
>>>> + * Note: AER must be enabled and supported by the device which must be
>>>> + * checked in advance, e.g. with pcie_aer_is_native().
>>>> + */
>>>> +void pci_aer_mask_internal_errors(struct pci_dev *dev)
>>>> +{
>>>> + int aer = dev->aer_cap;
>>>> + u32 mask;
>>>> +
>>>> + pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
>>>> + mask |= PCI_ERR_UNC_INTN;
>>>> + pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
>>>> +
>>> It does an extra clear we don't need, but....
>>> pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
>>> 0, PCI_ERR_UNC_INTN);
>>>
>>> is at very least shorter than the above 3 lines.
>> Doing so will overwrite the existing mask. CXL normally only uses AER UIE/CIE but if the device
>> happens to lose alternate training and no longer identifies as a CXL device than this mask
>> value would be critical for reporting PCI AER errors and would need UCE/CE enabled (other
>> than UIE/CIE).
> I'm not seeing that. Implementation of pci_clear_and_set_config_dword() is:
> void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
> u32 clear, u32 set)
> {
> u32 val;
>
> pci_read_config_dword(dev, pos, &val);
> val &= ~clear;
> val |= set;
> pci_write_config_dword(dev, pos, val);
> }
>
> With clear parameter as zero it will do the same the open coded
> version you have above as the ~clear will be all 1s and hence
> &= ~clear has no affect.
>
> Arguably we could add pci_clear_config_dword() and pci_set_config_dword()
> that both take one fewer parameter but I guess that is not worth
> the bother.
>
> Jonathan
>
Got it. I'll change to use pci_clear_and_set_config_dword().
-Terry
>
next prev parent reply other threads:[~2025-04-24 16:37 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-27 1:47 [PATCH v8 00/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-03-27 1:47 ` [PATCH v8 01/16] PCI/CXL: Introduce PCIe helper function pcie_is_cxl() Terry Bowman
2025-03-27 15:11 ` Ira Weiny
2025-03-27 15:30 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 02/16] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-03-27 16:48 ` Bjorn Helgaas
2025-03-27 17:15 ` Bowman, Terry
2025-03-27 17:49 ` Bjorn Helgaas
2025-03-27 16:58 ` Ira Weiny
2025-03-27 17:17 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 03/16] CXL/AER: Introduce Kfifo for forwarding CXL errors Terry Bowman
2025-03-27 17:08 ` Bjorn Helgaas
2025-03-27 18:12 ` Bowman, Terry
2025-03-28 17:02 ` Bjorn Helgaas
2025-03-28 17:36 ` Bowman, Terry
2025-03-28 17:01 ` Ira Weiny
2025-04-07 13:43 ` Bowman, Terry
2025-04-04 16:53 ` Jonathan Cameron
2025-04-23 14:33 ` Jonathan Cameron
2025-04-23 15:04 ` Jonathan Cameron
2025-04-23 22:12 ` Gregory Price
2025-03-27 1:47 ` [PATCH v8 04/16] cxl/aer: AER service driver forwards CXL error to CXL driver Terry Bowman
2025-03-27 17:13 ` Bjorn Helgaas
2025-04-07 14:00 ` Bowman, Terry
2025-04-23 15:04 ` Jonathan Cameron
2025-04-24 14:17 ` Bowman, Terry
2025-04-25 13:18 ` Jonathan Cameron
2025-04-25 21:03 ` Bowman, Terry
2025-05-15 21:52 ` Bowman, Terry
2025-05-20 11:04 ` Jonathan Cameron
2025-05-20 13:21 ` Bowman, Terry
2025-05-21 18:34 ` Jonathan Cameron
2025-05-21 23:30 ` Bowman, Terry
2025-04-23 22:21 ` Gregory Price
2025-03-27 1:47 ` [PATCH v8 05/16] PCI/AER: CXL driver dequeues CXL error forwarded from AER service driver Terry Bowman
2025-03-27 4:43 ` kernel test robot
2025-04-23 16:28 ` Jonathan Cameron
2025-04-24 15:03 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 06/16] CXL/PCI: Introduce CXL uncorrectable protocol error 'recovery' Terry Bowman
2025-03-27 3:37 ` kernel test robot
2025-03-27 4:19 ` kernel test robot
2025-04-23 16:35 ` Jonathan Cameron
2025-04-24 14:22 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 07/16] cxl/pci: Move existing CXL RAS initialization to CXL's cxl_port driver Terry Bowman
2025-04-17 10:18 ` Jonathan Cameron
2025-04-24 14:25 ` Bowman, Terry
2025-05-12 14:47 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 08/16] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-03-27 1:47 ` [PATCH v8 09/16] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-03-27 1:47 ` [PATCH v8 10/16] cxl/pci: Add log message if RAS registers are not mapped Terry Bowman
2025-04-23 16:41 ` Jonathan Cameron
2025-04-24 14:30 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 11/16] cxl/pci: Unifi CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-04-23 16:44 ` Jonathan Cameron
2025-05-07 16:28 ` Shiju Jose
2025-05-07 18:30 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 12/16] cxl/pci: Assign CXL Port protocol error handlers Terry Bowman
2025-04-23 16:47 ` Jonathan Cameron
2025-03-27 1:47 ` [PATCH v8 13/16] cxl/pci: Assign CXL Endpoint " Terry Bowman
2025-03-27 19:46 ` kernel test robot
2025-04-23 16:49 ` Jonathan Cameron
2025-03-27 1:47 ` [PATCH v8 14/16] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-04-17 17:22 ` Jonathan Cameron
2025-03-27 1:47 ` [PATCH v8 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-04-04 17:05 ` Jonathan Cameron
2025-04-07 14:34 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 16/16] CXL/PCI: Disable CXL protocol errors during CXL Port cleanup Terry Bowman
2025-03-28 1:18 ` kernel test robot
2025-04-04 17:04 ` Jonathan Cameron
2025-04-07 14:25 ` Bowman, Terry
2025-04-17 10:13 ` Jonathan Cameron
2025-04-24 16:37 ` Bowman, Terry [this message]
2025-03-27 17:16 ` [PATCH v8 00/16] Enable CXL PCIe port protocol error handling and logging Bjorn Helgaas
2025-03-27 22:04 ` Bowman, Terry
2025-05-06 23:06 ` Gregory Price
2025-05-07 18:28 ` Bowman, Terry
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