From: Alejandro Lucero Palau <alucerop@amd.com>
To: Dan Williams <dan.j.williams@intel.com>,
linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org,
pabeni@redhat.com, edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v10 01/26] cxl: make memdev creation type agnostic
Date: Thu, 20 Feb 2025 18:17:06 +0000 [thread overview]
Message-ID: <390c6b69-bbf4-47cb-95d9-215a92ee3cbf@amd.com> (raw)
In-Reply-To: <67b5421cd91d2_2d2c294ad@dwillia2-xfh.jf.intel.com.notmuch>
On 2/19/25 02:29, Dan Williams wrote:
> Alejandro Lucero Palau wrote:
>> On 2/6/25 19:37, Dan Williams wrote:
>>>
>>> I was envisioning that accelerators only consider 'struct cxl_dev_state'
>>> and that 'struct cxl_memdev_state' is exclusively for
>>> CXL_DEVTYPE_CLASSMEM memory expander use case.
>>
>> That was the original idea and what I have followed since the RFC, but
>> since the patchset has gone through some assumptions which turned wrong,
>> I seized the "revolution" for changing this as well.
>>
>>
>> A type2 is a memdev, and what makes it different is the exposure, so I
>> can not see why an accel driver, at least a Type2, should not use a
>> cxl_memdev_state struct. This simplifies the type2 support and after
>> all, a Type2 could require the exact same things like a type3, like
>> mbox, perf, poison, ... .
> I disagree, I think it avoids the discipline of maintaining Accelerator
> CXL.mem infrastructure alongside the sometimes super-set sometimes
> disjoint-set of generic CXL memory expander support.
>
> Specifically, the reason I think the implementation is worse off reusing
> cxl_memdev_state for accelerators is because accelerators are not
> subject to the same requirements as "memory device" expanders that emit
> the class code from CXL 3.1 8.1.12.1 "PCI Header - Class Code Register
> (Offset 09h)".
>
> The whole point of the CXL_DEVTYPE_CLASSMEM vs CXL_DEVTYPE_DEVMEM
> distinction was for cases where accelerators are not mandated to support
> the same functionality as a generic expander.
>
> It is not until patch12 that this set notices that to_cxl_memdev_state()
> has been returning NULL for accelerator created 'cxl_memdev_state'
> instances. However, patch12 is confused because to_cxl_memdev_state()
> has no reason to exist if it can be assumed that 'struct
> cxl_memdev_state' always wraps 'struct cxl_dev_state'.
>
> The fact that it requires thought and care to decide how accelerators
> can share code paths with the generic memory class device case is a
> *feature*.
>
> So either 'enum cxl_devtype' needs to be removed altogether (would need
> a strong argument that is currently absent from this set), or we need to
> carefully think about the optional functionality that an accelerator may
> want to reuse from expanders. As it stands, most of cxl_memdev_state
> makes little sense for an accelerator:
OK. I'll go back to using cxl_dev_state. More about this below.
>>> Something roughly like
>>> the below. Note, this borrows from the fwctl_alloc_device() example
>>> which captures the spirit of registering a c4ore object wrapped by an end
>>> driver provided structure).
>>>
>>> #define cxl_dev_state_create(parent, serial, dvsec, type, drv_struct, member) \
>>> ({ \
>>> static_assert(__same_type(struct cxl_dev_state, \
>>> ((drv_struct *)NULL)->member)); \
>>> static_assert(offsetof(drv_struct, member) == 0); \
>>> (drv_struct *)_cxl_dev_state_create(parent, serial, dvsec, \
>>> type, sizeof(drv_struct)); \
>>> })
>>
>> If you prefer the accel driver keeping a struct embedding the core cxl
>> object, that is fine. I can not see a reason for not doing it, although
>> I can not see a reason either for imposing this.
> The cxl_pci driver would use it to align on a single way to wrap its class device
> driver context around 'struct cxl_dev_state'. So it is more about
> setting common expectations across cxl_pci and accelerator drivers for
> how they wrap 'struct cxl_dev_state'.
>
> [..]
I have tried this but it is not so simple as with the fwctl case where
the embedded struct is simpler.
As a result, a good bunch of until now internal CXL structs need to go
to include/cxl/cxl.h, otherwise the size for the whole accel driver
struct embedding cxl_dev_state can not be known.
That makes those struct visible to accel drivers which we tried to
avoid, but I guess this is fine and we should ensure accel drivers do
not use those structs freely, whatever the reason.
I will post a RFC just with that change, so only first two patches of
the whole type2 support patchset. Let's be sure we agree on how the
accel driver does this first initialization before I send the whole
patchset again.
next prev parent reply other threads:[~2025-02-20 18:17 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 15:19 [PATCH v10 00/26] cxl: add type2 device basic support alucerop
2025-02-05 15:19 ` [PATCH v10 01/26] cxl: make memdev creation type agnostic alucerop
2025-02-06 19:37 ` Dan Williams
2025-02-17 12:32 ` Alejandro Lucero Palau
2025-02-19 2:29 ` Dan Williams
2025-02-20 18:17 ` Alejandro Lucero Palau [this message]
2025-02-17 13:05 ` Alejandro Lucero Palau
2025-02-13 3:57 ` Alison Schofield
2025-02-17 12:49 ` Alejandro Lucero Palau
2025-02-17 13:06 ` Alejandro Lucero Palau
2025-02-14 17:02 ` Jonathan Cameron
2025-02-17 13:08 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 02/26] sfc: add basic cxl initialization alucerop
2025-02-06 1:37 ` Edward Cree
2025-02-07 12:48 ` Simon Horman
2025-02-17 13:10 ` Alejandro Lucero Palau
2025-02-07 13:03 ` Simon Horman
2025-02-17 13:11 ` Alejandro Lucero Palau
2025-02-18 13:32 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 03/26] cxl: move pci generic code alucerop
2025-02-05 21:33 ` Ira Weiny
2025-02-06 17:49 ` Alejandro Lucero Palau
2025-02-14 17:11 ` Jonathan Cameron
2025-02-17 13:13 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 04/26] cxl: move register/capability check to driver alucerop
2025-02-07 12:52 ` Simon Horman
2025-02-17 13:17 ` Alejandro Lucero Palau
2025-02-14 17:21 ` Jonathan Cameron
2025-02-17 13:18 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 05/26] cxl: add function for type2 cxl regs setup alucerop
2025-02-05 21:35 ` Ira Weiny
2025-02-06 17:50 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 06/26] sfc: use cxl api for regs setup and checking alucerop
2025-02-05 21:31 ` Ira Weiny
2025-02-06 17:47 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 07/26] cxl: add support for setting media ready by an accel driver alucerop
2025-02-05 21:42 ` Ira Weiny
2025-02-06 17:58 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 08/26] sfc: set cxl media ready alucerop
2025-02-05 15:19 ` [PATCH v10 09/26] cxl: support device identification without mailbox alucerop
2025-02-05 21:45 ` Ira Weiny
2025-02-06 18:10 ` Alejandro Lucero Palau
2025-02-06 19:23 ` Ira Weiny
2025-02-17 13:41 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 alucerop
2025-02-05 15:19 ` [PATCH v10 11/26] sfc: initialize dpa resources alucerop
2025-02-05 15:19 ` [PATCH v10 12/26] cxl: prepare memdev creation for type2 alucerop
2025-02-05 15:19 ` [PATCH v10 13/26] sfc: create type2 cxl memdev alucerop
2025-02-05 15:19 ` [PATCH v10 14/26] cxl: define a driver interface for HPA free space enumeration alucerop
2025-02-07 12:55 ` Simon Horman
2025-02-17 13:44 ` Alejandro Lucero Palau
2025-02-13 4:08 ` Alison Schofield
2025-02-17 13:49 ` Alejandro Lucero Palau
2025-02-05 15:19 ` [PATCH v10 15/26] sfc: obtain root decoder with enough HPA free space alucerop
2025-02-05 22:47 ` Ira Weiny
2025-02-17 13:54 ` Alejandro Lucero Palau
2025-02-18 0:03 ` Ira Weiny
2025-02-05 15:19 ` [PATCH v10 16/26] cxl: define a driver interface for DPA allocation alucerop
2025-02-06 19:11 ` kernel test robot
2025-02-07 13:46 ` Simon Horman
2025-02-17 14:08 ` Alejandro Lucero Palau
2025-02-18 13:34 ` Simon Horman
2025-02-18 14:09 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 17/26] sfc: get endpoint decoder alucerop
2025-02-05 15:19 ` [PATCH v10 18/26] cxl: make region type based on endpoint type alucerop
2025-02-05 15:19 ` [PATCH v10 19/26] cxl/region: factor out interleave ways setup alucerop
2025-02-05 15:19 ` [PATCH v10 20/26] cxl/region: factor out interleave granularity setup alucerop
2025-02-05 15:19 ` [PATCH v10 21/26] cxl: allow region creation by type2 drivers alucerop
2025-02-06 20:06 ` kernel test robot
2025-02-07 13:23 ` Simon Horman
2025-02-05 15:19 ` [PATCH v10 22/26] cxl: add region flag for precluding a device memory to be used for dax alucerop
2025-02-05 15:19 ` [PATCH v10 23/26] sfc: create cxl region alucerop
2025-02-05 15:19 ` [PATCH v10 24/26] cxl: add function for obtaining region range alucerop
2025-02-05 15:19 ` [PATCH v10 25/26] sfc: update MCDI protocol headers alucerop
2025-02-05 15:19 ` [PATCH v10 26/26] sfc: support pio mapping based on cxl alucerop
2025-02-13 1:51 ` [PATCH v10 00/26] cxl: add type2 device basic support Alison Schofield
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