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(Jonathan) > - Change patch 7 subject to just: "cxl/port: Map Port RAS registers" > since it is only introducing a helper that is later used in the > endpoint case. (Jonathan) > > [1]: http://lore.kernel.org/20260122033330.1622168-1-dan.j.williams@intel.com > > Original cover letter: > > --- > > The CXL Port Protocol error handling series grew to be over 30 patches > which is too much to handle at once given the various topics involved. > One of the sub-threads of the v14 review was confusion about the new > devres groups to manage port setup unwind failures [2]. > > [2]: http://lore.kernel.org/20260115144605.00000666@huawei.com > > Given that review indicated a need to break up and better explain the > conversion, do that in a separate patch set. Build on top of the first > 18 patches of that series [3] that are ready to merge. > > [3]: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/log/?h=for-7.0/cxl-aer-prep > > The wider goals of the port protocol handling series are: > > 1/ Be minimally invasive to the ongoing maintenance burden of PCIe error > handling. Just do the minimal enlightenment to forward "internal" > errors for device with active CXL links to the CXL core. > > 2/ Build a framework for any driver that registers a 'struct cxl_memdev' > (or in the future a 'struct cxl_cachedev') gets protocol error > handling support. > > This "Unify RAS setup across port types" set supports goal 2/. It > enables a model where all CXL error handling is relative to the common > 'struct cxl_port' and 'struct cxl_dport' objects and is agnostic to > whether those objects are in support of the memory expansion class > device (driven by cxl_pci) or any other CXL endpoint in the system that > supports CXL.cachemem operation. > > In support of that unification, the setup of RAS registers needs to be > centralized. That in turn requires new handling for early exit setup > failures and additional teardown support for resources optionally > acquired at port / dport creation time. > > The devres group mechanism is deployed to cleanup some open coded > devm_release_action() calls. The devres group facility also comes in > handy for unwinding conditional setup steps in the port creation > process. Recall that ports defer probing their CXL resources until after > they are known to have a downstream CXL connection. So, early exit during > setup of a new dport may have more or less work to do depending on > whether the first or subsequent dport is being added. > > Given probing port resources is a 'probe' action it fits more naturally > as a driver operation. If cxl_port_add_dport() then moves to cxl_port > driver operation alongside ->probe(), it enables a cxl_test cleanup. The > cxl_test approach has a hard time mocking interfaces that are internal > to the cxl_core. > > The rest of the patches in this set finish off the conversion of 'struct > cxl_port' and 'struct cxl_dport' to be the only CXL objects that > interact with the CXL RAS. > > Dan Williams (8): > cxl/port: Cleanup handling of the nr_dports 0 -> 1 transition > cxl/port: Reduce number of @dport variables in cxl_port_add_dport() > cxl/port: Cleanup dport removal with a devres group > cxl/port: Move decoder setup before dport creation > cxl/port: Move dport probe operations to a driver event > cxl/port: Move dport RAS setup to dport add time > cxl/port: Move endpoint component register management to cxl_port > cxl/port: Unify endpoint and switch port lookup > > Terry Bowman (1): > cxl/port: Map Port RAS registers > > drivers/cxl/core/core.h | 10 ++ > drivers/cxl/cxl.h | 33 +++--- > drivers/cxl/cxlmem.h | 4 +- > drivers/cxl/cxlpci.h | 12 +- > tools/testing/cxl/exports.h | 13 --- > drivers/cxl/core/hdm.c | 6 +- > drivers/cxl/core/pci.c | 8 +- > drivers/cxl/core/port.c | 159 +++++++++++++++++---------- > drivers/cxl/core/ras.c | 50 ++++++--- > drivers/cxl/mem.c | 2 - > drivers/cxl/pci.c | 63 +---------- > drivers/cxl/port.c | 122 ++++++++++++++++++++ > tools/testing/cxl/cxl_core_exports.c | 22 ---- > tools/testing/cxl/test/mock.c | 36 ++---- > tools/testing/cxl/Kbuild | 3 +- > 15 files changed, 310 insertions(+), 233 deletions(-) > delete mode 100644 tools/testing/cxl/exports.h > > > base-commit: 9a8920ca8ebfb99604f639e7fbc681d0d04518a0 Hi Dan, I rebased my CXL port error handling series onto your series and completed testing with no issues. I tested using a single‑switch topology consisting of one root port (RP), one upstream port (USP), four downstream ports (DSPs), and four endpoints (EPs). Testing followed the error‑handling series test procedure. I injected AER errors using the aer_inject tool and simulated RAS error presence with a debug patch. All CXL devices were correctly discovered and populated in the topology. Protocol error tests passed on each CXL device, and I did not observe any regressions. Please feel free to include my tested sign‑off: Tested-by: Terry Bowman -Terry