From: Dave Jiang <dave.jiang@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org, dan.j.williams@intel.com,
ira.weiny@intel.com, vishal.l.verma@intel.com,
alison.schofield@intel.com, rafael@kernel.org,
bhelgaas@google.com, robert.moore@intel.com
Subject: Re: [PATCH 08/18] cxl: Add support for _DSM Function for retrieving QTG ID
Date: Tue, 14 Feb 2023 14:07:23 -0700 [thread overview]
Message-ID: <507beca0-70b1-f8f7-bbce-2ea2957999c0@intel.com> (raw)
In-Reply-To: <20230209140217.00002d22@Huawei.com>
On 2/9/23 7:02 AM, Jonathan Cameron wrote:
> On Mon, 06 Feb 2023 13:50:33 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>> CXL spec v3.0 9.17.3 CXL Root Device Specific Methods (_DSM)
>>
>> Add support to retrieve QTG ID via ACPI _DSM call. The _DSM call requires
>> an input of an ACPI package with 4 dwords (read latency, write latency,
>> read bandwidth, write bandwidth). The call returns a package with 1 WORD
>> that provides the max supported QTG ID and a package that may contain 0 or
>> more WORDs as the recommended QTG IDs in the recommended order.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> A few minor bits inline.
>
> Jonathan
>
>> ---
>> drivers/cxl/core/Makefile | 1
>> drivers/cxl/core/acpi.c | 99 +++++++++++++++++++++++++++++++++++++++++++++
>> drivers/cxl/cxl.h | 15 +++++++
>> 3 files changed, 115 insertions(+)
>> create mode 100644 drivers/cxl/core/acpi.c
>>
>> diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
>> index 438ce27faf77..11ccc2016ab7 100644
>> --- a/drivers/cxl/core/Makefile
>> +++ b/drivers/cxl/core/Makefile
>> @@ -11,4 +11,5 @@ cxl_core-y += mbox.o
>> cxl_core-y += pci.o
>> cxl_core-y += hdm.o
>> cxl_core-y += cdat.o
>> +cxl_core-y += acpi.o
>> cxl_core-$(CONFIG_CXL_REGION) += region.o
>> diff --git a/drivers/cxl/core/acpi.c b/drivers/cxl/core/acpi.c
>> new file mode 100644
>> index 000000000000..86dc6c9c1f24
>> --- /dev/null
>> +++ b/drivers/cxl/core/acpi.c
>> @@ -0,0 +1,99 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
>> +#include <linux/module.h>
>> +#include <linux/device.h>
>> +#include <linux/kernel.h>
>> +#include <linux/acpi.h>
>> +#include <linux/pci.h>
>> +#include <asm/div64.h>
>> +#include "cxlpci.h"
>> +#include "cxl.h"
>> +
>> +const guid_t acpi_cxl_qtg_id_guid =
>> + GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
>> + 0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
>> +
>> +/**
>> + * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
>> + * @handle: ACPI handle
>> + * @input: bandwidth and latency data
>> + *
>> + * Issue QTG _DSM with accompanied bandwidth and latency data in order to get
>> + * the QTG IDs that falls within the performance data.
>> + */
>> +struct qtg_dsm_output *cxl_acpi_evaluate_qtg_dsm(acpi_handle handle,
>> + struct qtg_dsm_input *input)
>> +{
>> + struct qtg_dsm_output *output;
>> + union acpi_object *out_obj, *out_buf, *pkg, in_buf, in_obj;
>
> Reorder to reverse Xmas tree perhaps.
Ok
>
>> + int len;
>> + int rc;
> Might as well put those on one line.
Ok
>
>> +
>> + in_obj.type = ACPI_TYPE_PACKAGE;
>> + in_obj.package.count = 1;
>> + in_obj.package.elements = &in_buf;
>> + in_buf.type = ACPI_TYPE_BUFFER;
>> + in_buf.buffer.pointer = (u8 *)input;
>> + in_buf.buffer.length = sizeof(u32) * 4;
> c99 style is nicer to read.
Ok
>
> union acpi_object in_obj = {
> .type =
>
> }
>> +
>> + out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
>> + if (!out_obj)
>> + return ERR_PTR(-ENXIO);
>> +
>> + if (out_obj->type != ACPI_TYPE_PACKAGE) {
>> + rc = -ENXIO;
>> + goto err;
>> + }
>> +
>> + /*
>> + * CXL spec v3.0 9.17.3.1
>> + * There should be 2 elements in the package. 1 WORD for max QTG ID supported
>> + * by the platform, and the other a package of recommended QTGs
>> + */
>> + if (out_obj->package.count != 2) {
>
> This stuff is usually designed to be extensible - tends to be explicitly allowed in
> stuff in the ACPI spec (not mentioned AFAICT in the CXL spec). So I'd be tempted to allow
>> 2 just don't read them.
Will remove check.
>
> if (out_obj->package.count < 2) {
>> + rc = -ENXIO;
>> + goto err;
>> + }
>> +
>> + pkg = &out_obj->package.elements[1];
>> + if (pkg->type != ACPI_TYPE_PACKAGE) {
>> + rc = -ENXIO;
>> + goto err;
>> + }
>> +
>> + out_buf = &pkg->package.elements[0];
>> + if (out_buf->type != ACPI_TYPE_BUFFER) {
>> + rc = -ENXIO;
>> + goto err;
>> + }
>> +
>> + len = out_buf->buffer.length;
>> + output = kmalloc(len + sizeof(*output), GFP_KERNEL);
>> + if (!output) {
>> + rc = -ENOMEM;
>> + goto err;
>> + }
>> +
>> + /* It's legal to have 0 QTG entries */
>> + if (len == 0) {
>> + output->nr = 0;
>> + goto out;
>> + }
>> +
>> + /* Malformed package, not multiple of WORD size */
>> + if (len % sizeof(u16)) {
>> + rc = -ENXIO;
>> + goto out;
>> + }
>> +
>> + output->nr = len / sizeof(u16);
>> + memcpy(output->qtg_ids, out_buf->buffer.pointer, len);
>
> Worth checking them against Max Support QTG ID as provided in the
> outer package? Obviously if they are greater than that there is
> a bug, but meh.
Ok will add check and warn.
>
>> +out:
>> + ACPI_FREE(out_obj);
>> + return output;
>> +
>> +err:
>> + ACPI_FREE(out_obj);
>> + return ERR_PTR(rc);
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_acpi_evaluate_qtg_dsm, CXL);
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index 849b22236f1d..e70df07f9b4b 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -719,6 +719,21 @@ int cdat_table_parse_dslbis(void *table, cdat_tbl_entry_handler handler,
>> int cxl_dsmas_parse_entry(struct acpi_cdat_header *header, void *arg);
>> int cxl_dslbis_parse_entry(struct acpi_cdat_header *header, void *arg);
>>
>> +struct qtg_dsm_input {
>> + u32 rd_lat;
>> + u32 wr_lat;
>> + u32 rd_bw;
>> + u32 wr_bw;
>> +};
>> +
>> +struct qtg_dsm_output {
>> + int nr;
>> + u16 qtg_ids[];
>> +};
>> +
>> +struct qtg_dsm_output *cxl_acpi_evaluate_qtg_dsm(acpi_handle handle,
>> + struct qtg_dsm_input *input);
>> +
>> /*
>> * Unit test builds overrides this to __weak, find the 'strong' version
>> * of these symbols in tools/testing/cxl/.
>>
>>
>
next prev parent reply other threads:[~2023-02-14 21:07 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 20:49 [PATCH 00/18] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-02-06 20:49 ` [PATCH 01/18] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-02-06 20:49 ` [PATCH 02/18] ACPICA: Export acpi_ut_verify_cdat_checksum() Dave Jiang
2023-02-07 14:19 ` Rafael J. Wysocki
2023-02-07 15:47 ` Dave Jiang
2023-02-09 11:30 ` Jonathan Cameron
2023-02-06 20:49 ` [PATCH 03/18] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-02-09 11:34 ` Jonathan Cameron
2023-02-09 17:31 ` Dave Jiang
2023-02-06 20:49 ` [PATCH 04/18] cxl: Add common helpers for cdat parsing Dave Jiang
2023-02-09 11:58 ` Jonathan Cameron
2023-02-09 22:57 ` Dave Jiang
2023-02-11 10:18 ` Lukas Wunner
2023-02-14 13:17 ` Jonathan Cameron
2023-02-14 20:36 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 05/18] ACPICA: Fix 'struct acpi_cdat_dsmas' spelling mistake Dave Jiang
2023-02-06 22:00 ` Lukas Wunner
2023-02-06 20:50 ` [PATCH 06/18] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-02-09 13:29 ` Jonathan Cameron
2023-02-13 22:55 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 07/18] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-02-09 13:50 ` Jonathan Cameron
2023-02-14 0:24 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 08/18] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-02-09 14:02 ` Jonathan Cameron
2023-02-14 21:07 ` Dave Jiang [this message]
2023-02-06 20:50 ` [PATCH 09/18] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-02-09 14:10 ` Jonathan Cameron
2023-02-14 21:29 ` Dave Jiang
2023-02-06 20:50 ` [PATCH 10/18] PCI: Export pcie_get_speed() using the code from sysfs PCI link speed show function Dave Jiang
2023-02-06 22:27 ` Lukas Wunner
2023-02-07 20:29 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 11/18] PCI: Export pcie_get_width() using the code from sysfs PCI link width " Dave Jiang
2023-02-06 22:43 ` Bjorn Helgaas
2023-02-07 20:35 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 12/18] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-02-06 22:39 ` Bjorn Helgaas
2023-02-07 20:51 ` Dave Jiang
2023-02-08 22:15 ` Bjorn Helgaas
2023-02-08 23:56 ` Dave Jiang
2023-02-09 15:10 ` Jonathan Cameron
2023-02-14 22:22 ` Dave Jiang
2023-02-15 12:13 ` Jonathan Cameron
2023-02-22 17:54 ` Dave Jiang
2023-02-09 15:16 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 13/18] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-02-09 15:24 ` Jonathan Cameron
2023-02-14 23:03 ` Dave Jiang
2023-02-15 13:17 ` Jonathan Cameron
2023-02-15 16:38 ` Dave Jiang
2023-02-06 20:51 ` [PATCH 14/18] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 15/18] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-02-09 15:29 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 16/18] cxl: Move reading of CDAT data from device to after media is ready Dave Jiang
2023-02-06 22:17 ` Lukas Wunner
2023-02-07 20:55 ` Dave Jiang
2023-02-09 15:31 ` Jonathan Cameron
2023-02-06 20:51 ` [PATCH 17/18] cxl: Attach QTG IDs to the DPA ranges for the device Dave Jiang
2023-02-09 15:34 ` Jonathan Cameron
2023-02-06 20:52 ` [PATCH 18/18] cxl: Export sysfs attributes for device QTG IDs Dave Jiang
2023-02-09 15:41 ` Jonathan Cameron
2023-03-23 23:20 ` Dan Williams
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