From: Shiyang Ruan <ruansy.fnst@fujitsu.com>
To: Dan Williams <dan.j.williams@intel.com>,
qemu-devel@nongnu.org, linux-cxl@vger.kernel.org
Cc: Jonathan.Cameron@huawei.com, dave@stgolabs.net,
ira.weiny@intel.com, stable@vger.kernel.org
Subject: Re: [RFC PATCH v2 1/6] cxl/core: correct length of DPA field masks
Date: Mon, 1 Apr 2024 17:14:52 +0800 [thread overview]
Message-ID: <545f7629-2937-42ff-809e-02fdff5f4571@fujitsu.com> (raw)
In-Reply-To: <66076ce2ddec7_19e02946d@dwillia2-mobl3.amr.corp.intel.com.notmuch>
在 2024/3/30 9:37, Dan Williams 写道:
> Shiyang Ruan wrote:
>> The length of Physical Address in General Media Event Record/DRAM Event
>> Record is 64-bit, so the field mask should be defined as such length.
>> Otherwise, this causes cxl_general_media and cxl_dram tracepoints to
>> mask off the upper-32-bits of DPA addresses. The cxl_poison event is
>> unaffected.
>>
>> If userspace was doing its own DPA-to-HPA translation this could lead to
>> incorrect page retirement decisions, but there is no known consumer
>> (like rasdaemon) of this event today.
>>
>> Fixes: d54a531a430b ("cxl/mem: Trace General Media Event Record")
>> Cc: <stable@vger.kernel.org>
>> Cc: Dan Williams <dan.j.williams@intel.com>
>> Cc: Davidlohr Bueso <dave@stgolabs.net>
>> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Cc: Ira Weiny <ira.weiny@intel.com>
>> Signed-off-by: Shiyang Ruan <ruansy.fnst@fujitsu.com>
>> ---
>> drivers/cxl/core/trace.h | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
>> index e5f13260fc52..e2d1f296df97 100644
>> --- a/drivers/cxl/core/trace.h
>> +++ b/drivers/cxl/core/trace.h
>> @@ -253,11 +253,11 @@ TRACE_EVENT(cxl_generic_event,
>> * DRAM Event Record
>> * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
>> */
>> -#define CXL_DPA_FLAGS_MASK 0x3F
>> +#define CXL_DPA_FLAGS_MASK 0x3FULL
>
> This change makes sense...
>
>> #define CXL_DPA_MASK (~CXL_DPA_FLAGS_MASK)
>>
>> -#define CXL_DPA_VOLATILE BIT(0)
>> -#define CXL_DPA_NOT_REPAIRABLE BIT(1)
>> +#define CXL_DPA_VOLATILE BIT_ULL(0)
>> +#define CXL_DPA_NOT_REPAIRABLE BIT_ULL(1)
>
> ...these do not. The argument to __print_flags() is an unsigned long, so
> they will be cast down to (unsigned long), and they are never used as a
> mask so the generated code should not change.
They will only used to check if such flag is set, not used as mask. So,
yes, I'll remove these changes.
--
Thanks,
Ruan.
next prev parent reply other threads:[~2024-04-01 9:15 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 6:36 [RFC PATCH v2 0/6] cxl: add poison event handler Shiyang Ruan
2024-03-29 6:36 ` [RFC PATCH v2 1/6] cxl/core: correct length of DPA field masks Shiyang Ruan
2024-03-30 1:37 ` Dan Williams
2024-04-01 9:14 ` Shiyang Ruan [this message]
2024-03-29 6:36 ` [RFC PATCH v2 2/6] cxl/core: introduce cxl_mem_report_poison() Shiyang Ruan
2024-03-30 1:39 ` Dan Williams
2024-03-29 6:36 ` [RFC PATCH v2 3/6] cxl/core: add report option for cxl_mem_get_poison() Shiyang Ruan
2024-03-30 1:50 ` Dan Williams
2024-04-03 14:56 ` Shiyang Ruan
2024-04-04 13:46 ` Jonathan Cameron
2024-03-29 6:36 ` [RFC PATCH v2 4/6] cxl/core: report poison when injecting from debugfs Shiyang Ruan
2024-03-29 18:13 ` Alison Schofield
2024-03-30 1:52 ` Dan Williams
2024-04-03 15:07 ` Shiyang Ruan
2024-03-29 6:36 ` [RFC PATCH v2 5/6] cxl: add definition for transaction types Shiyang Ruan
2024-03-30 1:53 ` Dan Williams
2024-03-29 6:36 ` [RFC PATCH v2 6/6] cxl/core: add poison injection event handler Shiyang Ruan
2024-03-29 18:27 ` Alison Schofield
2024-03-29 17:43 ` [RFC PATCH v2 0/6] cxl: add poison " Alison Schofield
2024-03-29 18:22 ` Dan Williams
2024-03-29 19:38 ` Alison Schofield
2024-03-29 20:56 ` Dan Williams
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