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Thu, 15 Feb 2024 07:31:31 -0800 (PST) Received: from [192.168.69.100] ([176.187.193.50]) by smtp.gmail.com with ESMTPSA id bt21-20020a056000081500b0033d14455c99sm408546wrb.101.2024.02.15.07.31.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Feb 2024 07:31:30 -0800 (PST) Message-ID: <5b53790b-8f94-4b21-b1da-e7f278af0dd7@linaro.org> Date: Thu, 15 Feb 2024 16:31:26 +0100 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] target/i386: Enable page walking from MMIO memory Content-Language: en-US To: Jonathan Cameron , qemu-devel@nongnu.org, Peter Maydell , Gregory Price , =?UTF-8?Q?Alex_Benn=C3=A9e?= , Sajjan Rao , Dimitrios Palyvos , richard.henderson@linaro.org, Paolo Bonzini , Eduardo Habkost Cc: linux-cxl@vger.kernel.org References: <20240215150133.2088-1-Jonathan.Cameron@huawei.com> <20240215150133.2088-3-Jonathan.Cameron@huawei.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240215150133.2088-3-Jonathan.Cameron@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 15/2/24 16:01, Jonathan Cameron via wrote: > From: Gregory Price > > CXL emulation of interleave requires read and write hooks due to > requirement for subpage granularity. The Linux kernel stack now enables > using this memory as conventional memory in a separate NUMA node. If a > process is deliberately forced to run from that node > $ numactl --membind=1 ls > the page table walk on i386 fails. > > Useful part of backtrace: > > (cpu=cpu@entry=0x555556fd9000, fmt=fmt@entry=0x555555fe3378 "cpu_io_recompile: could not find TB for pc=%p") > at ../../cpu-target.c:359 > (retaddr=0, addr=19595792376, attrs=..., xlat=, cpu=0x555556fd9000, out_offset=) > at ../../accel/tcg/cputlb.c:1339 > (cpu=0x555556fd9000, full=0x7fffee0d96e0, ret_be=ret_be@entry=0, addr=19595792376, size=size@entry=8, mmu_idx=4, type=MMU_DATA_LOAD, ra=0) at ../../accel/tcg/cputlb.c:2030 > (cpu=cpu@entry=0x555556fd9000, p=p@entry=0x7ffff56fddc0, mmu_idx=, type=type@entry=MMU_DATA_LOAD, memop=, ra=ra@entry=0) at ../../accel/tcg/cputlb.c:2356 > (cpu=cpu@entry=0x555556fd9000, addr=addr@entry=19595792376, oi=oi@entry=52, ra=ra@entry=0, access_type=access_type@entry=MMU_DATA_LOAD) at ../../accel/tcg/cputlb.c:2439 > at ../../accel/tcg/ldst_common.c.inc:301 > at ../../target/i386/tcg/sysemu/excp_helper.c:173 > (err=0x7ffff56fdf80, out=0x7ffff56fdf70, mmu_idx=0, access_type=MMU_INST_FETCH, addr=18446744072116178925, env=0x555556fdb7c0) > at ../../target/i386/tcg/sysemu/excp_helper.c:578 > (cs=0x555556fd9000, addr=18446744072116178925, size=, access_type=MMU_INST_FETCH, mmu_idx=0, probe=, retaddr=0) at ../../target/i386/tcg/sysemu/excp_helper.c:604 > > Avoid this by plumbing the address all the way down from > x86_cpu_tlb_fill() where is available as retaddr to the actual accessors > which provide it to probe_access_full() which already handles MMIO accesses. > Suggested-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Gregory Price > > --- > Patch posted in reply to thread: > https://lore.kernel.org/qemu-devel/ZbvpSaOXzZkqDd6c@memverge.com/ > > I checked Gregory was fine with me adding Sign-off / author via the CXL discord. > --- > target/i386/tcg/sysemu/excp_helper.c | 57 +++++++++++++++------------- > 1 file changed, 30 insertions(+), 27 deletions(-)