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X-CSE-ConnectionGUID: qrZ8NPYiT12F1Rz6IDJhQw== X-CSE-MsgGUID: AU3Z+MnLQ1+5oEKul2LcQw== X-IronPort-AV: E=McAfee;i="6600,9927,11089"; a="13603282" X-IronPort-AV: E=Sophos;i="6.08,205,1712646000"; d="scan'208";a="13603282" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 11:06:10 -0700 X-CSE-ConnectionGUID: nu6jDm+xQ1OD17Mz7pfHcA== X-CSE-MsgGUID: J+uyWzaORDG7TpdBgnmCRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,205,1712646000"; d="scan'208";a="36181617" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [10.125.108.72]) ([10.125.108.72]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2024 11:06:10 -0700 Message-ID: <5de124d1-8c53-45c7-ab4b-17282c56d1b1@intel.com> Date: Fri, 31 May 2024 11:06:08 -0700 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] PCI: Warn on missing cfg_access_lock during secondary bus reset To: Dan Williams , bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org References: <171711745834.1628941.5259278474013108507.stgit@dwillia2-xfh.jf.intel.com> <171711746953.1628941.4692125082286867825.stgit@dwillia2-xfh.jf.intel.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <171711746953.1628941.4692125082286867825.stgit@dwillia2-xfh.jf.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/30/24 6:04 PM, Dan Williams wrote: > The recent adventure with adding lockdep tracking for cfg_access_lock, > while it yielded many false positives [1], it did catch a true positive in > the pci_reset_bus() path [2]. > > So, while lockdep is difficult to deploy, open coding a check that > cfg_access_lock is held during the reset is feasible. > > While this does not offer a full backtrace, it should be sufficient to > implicate the caller of pci_bridge_secondary_bus_reset() as a path that > needs investigation. > > Link: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134186v1/shard-dg2-1/igt@device_reset@unbind-reset-rebind.html [1] > Link: http://lore.kernel.org/r/cfb50601-5d2a-4676-a958-1bd3f1b06654@intel.com [2] > Cc: Dave Jiang > Cc: Bjorn Helgaas > Signed-off-by: Dan Williams Reviewed-by: Dave Jiang > --- > drivers/pci/pci.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 35fb1f17a589..8df32a3a0979 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -4883,6 +4883,9 @@ void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) > */ > int pci_bridge_secondary_bus_reset(struct pci_dev *dev) > { > + if (!dev->block_cfg_access) > + pci_warn_once(dev, "unlocked secondary bus reset via: %pS\n", > + __builtin_return_address(0)); > pcibios_reset_secondary_bus(dev); > > return pci_bridge_wait_for_secondary_bus(dev, "bus reset"); >