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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?14iuKlNdi1V/9lhtlbbxKg7R9jVvfv2CIElG5EEPTyeldd3/Yl57TQ+NU2BB?= =?us-ascii?Q?bkXuCmkvxRcsaTkiZ2cGUTG1IyiKIjQOZ28nHAPeoiUJJcGh3JwA9ZV0x1ou?= =?us-ascii?Q?74c5Xp3nEE1SkJxeBvuSzYSZbkc2K9NgLwgMkaZRbR47CRLONT4cmt1N+BXr?= =?us-ascii?Q?AESgF3vhUBK5+aCh7K2BNHZeD6ICPB9J4GlBZS6SITyWULATJV+6uCjo5h1z?= =?us-ascii?Q?OWwoAYAh0DBe1M/vyDHRI9/Azuvm3AlaNxgFBE7/9c42J1vPoG80ZcJF+t0l?= =?us-ascii?Q?o4NDP8x8c6HGMw4G5YTBaIym8zJ/Ppwd2+BQBggOr/Y10mTa7jNTTtJ7fJs8?= =?us-ascii?Q?Tdj/pxGMXZs5z0+86VFlMraVmI3+nJzceVeKFACqRlz9F8OPDGDK4LzaDshK?= =?us-ascii?Q?ggM7aepkWBFT60/oQ3rPKM86mfu9VixQbopFyNstqGhctLDo+aA1YOtha6vl?= =?us-ascii?Q?7FoDS4InUeHD2KeXBf6D9q+nOTZ3AQZqJvkDWGCP2REH504dSaiS139SO4M4?= =?us-ascii?Q?f2ePq4dA3LZWpHQw5+dmKAnilOpa1XWWIE+cmAHH0pOIgsgc2tOqL8583KUJ?= =?us-ascii?Q?I6xwEaR15+ugPGATpSe2enpDHh3mBDze3BYV5BGrngAK261ekWdahZI5+eni?= =?us-ascii?Q?MOpX2oIPVkWsaBAezCaylalkywWQDkKmVmV3FOWsIms8CeezGDnqncqJmMLL?= =?us-ascii?Q?JQjhgneA11/SOc01+PLQjthCadFDd79H6xV9b+9pZHsFkBV2CA83V40WB7MG?= =?us-ascii?Q?z8v0en8RfOPT6xBTXMOPlnEkKzUmf6bnAgNIvIo/OktrD9d1LZMnMJR+IIpy?= =?us-ascii?Q?P5hVxQ9u7gZUGCmSzQnNE1uohY0i1Y4yJqlg3O6g8vgM9lSytniT3svsjHEW?= =?us-ascii?Q?Ck1YjukHipdVOiOMMJpxfDqRPba3DY3L+yN8cYVhxMxjM82flZwu+p1/YNTI?= =?us-ascii?Q?M0RYudXhgmIDjcsxnescwB4GnAI1jj1UH0qqtnxUmRXteW4/E1W8Hht0hQR1?= =?us-ascii?Q?69xHxfYtIK/eS5Oh2dCSt/L1lZ4mMP53gmHiWDqNk8zbvSJ2D4ZSZNvnjwls?= =?us-ascii?Q?t7iwduZEgOlu+/kb5EuAhJNbpVTu0AW15UkjTQIfhDL8FofnJhznjdiCXaZ1?= =?us-ascii?Q?QNgeLrPeYmvLAiybPyE2ZqAIA/gxDhJmts94/4OtegqjisbCtym5i/skUnKV?= =?us-ascii?Q?pQQJUpEnh8H7MTXTCtrT4h/mc0s5VWVcCbF48rYrp/CnJX8gzQPTTilkhqIr?= =?us-ascii?Q?jUyM47f4mwEhzvH5a+06XWkvIHateliaFZNtuzA88JqNkypRlgc3TGKFF8VL?= =?us-ascii?Q?AIvaXQZxq0oSaHlKFK97f7qwgBs4TZCZi9G5PHoPFWqHHJ06Z43/7kFa9h4v?= =?us-ascii?Q?oJmjPjWeBD+dixH4ZGLQ0sr1eL4ZxiLDVp12RYNSJxWktlQqxjy1+Jos7jhc?= =?us-ascii?Q?sHhPFKZ9bWRCtoSyLbG++DDVwSyQsjjJEaGG0bBe3Buh7A6h5Lp16z0WLYuM?= =?us-ascii?Q?4pqtm2jyELz0yXXV5BANRU7hAtmq+wB6OVRHG5X54VSmAMePwVEARFPJgvlA?= =?us-ascii?Q?q10dxgvqzVX2HQUO0RPpC/aoiitJ4Z2XtPq13w93rvHqTf62okMrS3hDp506?= =?us-ascii?Q?SQ=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: a95e1358-813e-4517-f1ba-08da7bfe4234 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1101MB2126.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2022 01:01:59.0272 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9qLBNIyc8fHbQTd4sAvSvwlx9lAaUFGdKH2I9D5BOe8MuF9YcvSr8HX32rxPMV7fF/nXuzRqEShbXBgCGKPa67db8E0fEBBwxB5bIopUQ2w= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4143 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Dave Jiang wrote: > CXL spec v3.0 added 2 CAP bits to the CXL HDM Decoder Capability Register. > CXL spec v3.0 8.2.4.19.1. Bit 11 indicates that 3, 6, and 12 way interleave > is capable. Bit 12 indicates that 16 way interleave is capable. > > Add code to parse_hdm_decoder_caps() to cache those new bits. Add check in > cxl_interleave_verify() call to make sure those CAP bits matches the passed > in interleave value. > > Signed-off-by: Dave Jiang > --- > drivers/cxl/core/hdm.c | 6 ++++++ > drivers/cxl/cxl.h | 2 ++ > drivers/cxl/cxlmem.h | 13 +++++++++++++ > 3 files changed, 21 insertions(+) > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 8143e2615957..0baf3c4820a5 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -80,6 +80,12 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) > cxlhdm->interleave_mask |= GENMASK(11, 8); > if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap)) > cxlhdm->interleave_mask |= GENMASK(14, 12); > + > + cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_DEFAULT; > + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap)) > + cxlhdm->interleave_cap |= CXL_HDM_INTERLEAVE_CAP_3_6_12; > + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap)) > + cxlhdm->interleave_cap |= CXL_HDM_INTERLEAVE_CAP_16; > } > > static void __iomem *map_hdm_decoder_regs(struct cxl_port *port, > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index bc604b7e44fb..105d814941e7 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -42,6 +42,8 @@ > #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) > #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) > #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) > +#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) > +#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) > #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 > #define CXL_HDM_DECODER_ENABLE BIT(1) > #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index 625fce0b6c2c..ebd645d8bbb4 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -393,14 +393,24 @@ static inline void cxl_mem_active_dec(void) > } > #endif > > +#define CXL_HDM_INTERLEAVE_CAP_DEFAULT BIT(1) | BIT(2) | BIT(4) | BIT(8) > +#define CXL_HDM_INTERLEAVE_CAP_3_6_12 BIT(3) | BIT(6) | BIT(12) > +#define CXL_HDM_INTERLEAVE_CAP_16 BIT(16) > + > struct cxl_hdm { > struct cxl_component_regs regs; > unsigned int decoder_count; > unsigned int target_count; > unsigned int interleave_mask; > + unsigned long interleave_cap; > struct cxl_port *port; > }; > > +static inline bool valid_interleave_ways(struct cxl_hdm *cxlhdm, u8 iw) > +{ > + return test_bit(iw, &cxlhdm->interleave_cap); > +} I think "test_bit(iw, &cxlhdm->interleave_cap)" is self explanatory, no need for the valid_interleave_ways() wrapper. Other than that: Reviewed-by: Dan Williams