RE: [PATCH 2/2] cxl: export intereleave capability as port sysfs attribute

[Dan Williams <dan.j.williams@intel.com>]

Dave Jiang wrote:
> Export the interleave capability as a sysfs attribute for a port. The
> exported mask is interpreted from the CXL HDM Decoder Capability Register
> (CXL spec v 8.2.4.19.1). Each bit in the mask represents the number of
> interleave ways the decoder supports. For example, CXL devices designed
> from CXL spec v2.0 supports 1, 2, 4, and 8 interleave ways. The exported
> mask would show 0x116. The exported sysfs attribute will help user region
> creation to do more valid configuration checking.
> 
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  drivers/cxl/port.c |   13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index e3e93e1b663e..231cfe888918 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -135,8 +135,21 @@ static ssize_t interleave_mask_show(struct device *dev, struct device_attribute
>  }
>  static DEVICE_ATTR_RO(interleave_mask);
>  
> +static ssize_t interleave_cap_show(struct device *dev, struct device_attribute *attr,
> +				   char *buf)
> +{
> +	struct cxl_hdm *cxlhdm = dev_get_drvdata(dev);
> +
> +	if (!cxlhdm)
> +		return 0;

Similar Documentation + "delete this check" comments as patch1.