Linux CXL
 help / color / mirror / Atom feed
From: Dan Williams <dan.j.williams@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
	<nvdimm@lists.linux.dev>
Cc: <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
	<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
	<Jonathan.Cameron@huawei.com>, <dave@stgolabs.net>,
	<benjamin.cheatham@amd.com>
Subject: RE: [PATCH v5 18/18] cxl: add dimm_id support for __nvdimm_create()
Date: Tue, 29 Nov 2022 17:33:03 -0800	[thread overview]
Message-ID: <6386b2cf426ee_3cbe02946f@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <166863357043.80269.4337575149671383294.stgit@djiang5-desk3.ch.intel.com>

Dave Jiang wrote:
> Set the cxlds->serial as the dimm_id to be fed to __nvdimm_create(). The
> security code uses that as the key description for the security key of the
> memory device. The nvdimm unlock code cannot find the respective key
> without the dimm_id.
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  drivers/cxl/cxlmem.h         |    3 +++
>  drivers/cxl/pci.c            |    4 ++++
>  drivers/cxl/pmem.c           |    4 +++-
>  tools/testing/cxl/test/mem.c |    4 ++++
>  4 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 75baeb0bbe57..76bdec873868 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -178,6 +178,8 @@ struct cxl_endpoint_dvsec_info {
>  	struct range dvsec_range[2];
>  };
>  
> +#define CXL_DEV_ID_LEN 32
> +
>  /**
>   * struct cxl_dev_state - The driver device state
>   *
> @@ -244,6 +246,7 @@ struct cxl_dev_state {
>  
>  	resource_size_t component_reg_phys;
>  	u64 serial;
> +	u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */
>  
>  	struct xarray doe_mbs;
>  
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 621a0522b554..c48fcd2a90ef 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -456,6 +456,10 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>  		return PTR_ERR(cxlds);
>  
>  	cxlds->serial = pci_get_dsn(pdev);
> +	rc = snprintf(cxlds->dev_id, CXL_DEV_ID_LEN, "%llu", cxlds->serial);
> +	if (rc <= 0)
> +		return -ENXIO;
> +

Per below, move this to cxl_nvd, but also if you change the format
string to %#llx then you know you can reduce CXL_DEV_ID_LEN to 19
because a 64-bit number will never take more than 18 characters to
print.

>  	cxlds->cxl_dvsec = pci_find_dvsec_capability(
>  		pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
>  	if (!cxlds->cxl_dvsec)
> diff --git a/drivers/cxl/pmem.c b/drivers/cxl/pmem.c
> index 322f834cc27d..80556dc8d29c 100644
> --- a/drivers/cxl/pmem.c
> +++ b/drivers/cxl/pmem.c
> @@ -112,9 +112,11 @@ static int cxl_nvdimm_probe(struct device *dev)
>  	set_bit(ND_CMD_GET_CONFIG_SIZE, &cmd_mask);
>  	set_bit(ND_CMD_GET_CONFIG_DATA, &cmd_mask);
>  	set_bit(ND_CMD_SET_CONFIG_DATA, &cmd_mask);
> +
>  	nvdimm = __nvdimm_create(cxl_nvb->nvdimm_bus, cxl_nvd,
>  				 cxl_dimm_attribute_groups, flags,
> -				 cmd_mask, 0, NULL, NULL, cxl_security_ops, NULL);
> +				 cmd_mask, 0, NULL, cxlds->dev_id,
> +				 cxl_security_ops, NULL);

I would hang this off of cxl_nvd->dev_id, not cxlds->dev_id, since the
former is associated with the nvdimm side of a cxl_memdev.

>  	if (!nvdimm) {
>  		rc = -ENOMEM;
>  		goto out;
> diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
> index 38f1cea0a353..94a3f42096c8 100644
> --- a/tools/testing/cxl/test/mem.c
> +++ b/tools/testing/cxl/test/mem.c
> @@ -593,6 +593,10 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
>  		return PTR_ERR(cxlds);
>  
>  	cxlds->serial = pdev->id;
> +	rc = snprintf(cxlds->dev_id, CXL_DEV_ID_LEN, "%llu", cxlds->serial);
> +	if (rc <= 0)
> +		return -ENXIO;
> +
>  	cxlds->mbox_send = cxl_mock_mbox_send;
>  	cxlds->payload_size = SZ_4K;
>  
> 
> 



  reply	other threads:[~2022-11-30  1:33 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-16 21:17 [PATCH v5 00/18] Introduce security commands for CXL pmem device Dave Jiang
2022-11-16 21:17 ` [PATCH v5 01/18] cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation Dave Jiang
2022-11-16 21:17 ` [PATCH v5 02/18] tools/testing/cxl: Add "Get Security State" opcode support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 03/18] cxl/pmem: Add "Set Passphrase" security command support Dave Jiang
2022-11-30  0:51   ` Dan Williams
2022-11-16 21:18 ` [PATCH v5 04/18] tools/testing/cxl: Add "Set Passphrase" opcode support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 05/18] cxl/pmem: Add Disable Passphrase security command support Dave Jiang
2022-11-30  0:56   ` Dan Williams
2022-11-16 21:18 ` [PATCH v5 06/18] tools/testing/cxl: Add "Disable" security opcode support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 07/18] cxl/pmem: Add "Freeze Security State" security command support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 08/18] tools/testing/cxl: Add "Freeze Security State" security opcode support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 09/18] cxl/pmem: Add "Unlock" security command support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 10/18] tools/testing/cxl: Add "Unlock" security opcode support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 11/18] cxl/pmem: Add "Passphrase Secure Erase" security command support Dave Jiang
2022-11-16 21:18 ` [PATCH v5 12/18] tools/testing/cxl: Add "passphrase secure erase" opcode support Dave Jiang
2022-11-17 13:57   ` Jonathan Cameron
2022-11-18 22:07     ` [PATCH v6] " Dave Jiang
2022-11-16 21:19 ` [PATCH v5 13/18] nvdimm/cxl/pmem: Add support for master passphrase disable security command Dave Jiang
2022-11-16 21:19 ` [PATCH v5 14/18] cxl/pmem: add id attribute to CXL based nvdimm Dave Jiang
2022-11-30  1:07   ` Dan Williams
2022-11-16 21:19 ` [PATCH v5 15/18] tools/testing/cxl: add mechanism to lock mem device for testing Dave Jiang
2022-11-16 21:19 ` [PATCH v5 16/18] cxl/pmem: add provider name to cxl pmem dimm attribute group Dave Jiang
2022-11-30  1:12   ` Dan Williams
2022-11-16 21:19 ` [PATCH v5 17/18] libnvdimm: Introduce CONFIG_NVDIMM_SECURITY_TEST flag Dave Jiang
2022-11-30  1:26   ` Dan Williams
2022-11-16 21:19 ` [PATCH v5 18/18] cxl: add dimm_id support for __nvdimm_create() Dave Jiang
2022-11-30  1:33   ` Dan Williams [this message]
2022-11-18 18:56 ` [PATCH v5 00/18] Introduce security commands for CXL pmem device Davidlohr Bueso

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=6386b2cf426ee_3cbe02946f@dwillia2-xfh.jf.intel.com.notmuch \
    --to=dan.j.williams@intel.com \
    --cc=Jonathan.Cameron@huawei.com \
    --cc=alison.schofield@intel.com \
    --cc=benjamin.cheatham@amd.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=ira.weiny@intel.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=nvdimm@lists.linux.dev \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox