From: Dan Williams <dan.j.williams@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
Alison Schofield <alison.schofield@intel.com>, <rrichter@amd.com>,
<terry.bowman@amd.com>, <bhelgaas@google.com>,
<dave.jiang@intel.com>, <nvdimm@lists.linux.dev>
Subject: Re: [PATCH v6 11/12] tools/testing/cxl: Add an RCH topology
Date: Fri, 2 Dec 2022 23:50:22 -0800 [thread overview]
Message-ID: <638affbee7b98_3cbe0294f7@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20221202170407.0000030e@Huawei.com>
Jonathan Cameron wrote:
> On Thu, 01 Dec 2022 13:34:21 -0800
> Dan Williams <dan.j.williams@intel.com> wrote:
>
> > In an RCH topology a CXL host-bridge as Root Complex Integrated Endpoint
> > the represents the memory expander. Unlike a VH topology there is no
> > CXL/PCIE Root Port that host the endpoint. The CXL subsystem maps this
> > as the CXL root object (ACPI0017 on ACPI based systems) targeting the
> > host-bridge as a dport, per usual, but then that dport directly hosts
> > the endpoint port.
> >
> > Mock up that configuration with a 4th host-bridge that has a 'cxl_rcd'
> > device instance as its immediate child.
> >
> > Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
>
> A few trivial things inline.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
>
>
> > -static struct pci_bus mock_pci_bus[NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST];
> > +static struct pci_bus mock_pci_bus[NR_BRIDGES];
> > static struct acpi_pci_root mock_pci_root[ARRAY_SIZE(mock_pci_bus)] = {
> > [0] = {
> > .bus = &mock_pci_bus[0],
> > @@ -452,7 +493,9 @@ static struct acpi_pci_root mock_pci_root[ARRAY_SIZE(mock_pci_bus)] = {
> > [2] = {
> > .bus = &mock_pci_bus[2],
> > },
> > -
>
> I guess fixing this stray space here is fine to avoid a rebase to tidy it up
> in original patch which you have on your next branch.
In fact it's already upstream in v6.1-rc4 unfortunately, but it has no
business being in this patch.
So the hunk is now:
@@ -452,6 +493,9 @@ static struct acpi_pci_root mock_pci_root[ARRAY_SIZE(mock_pci_bus)] = {
[2] = {
.bus = &mock_pci_bus[2],
},
+ [3] = {
+ .bus = &mock_pci_bus[3],
+ },
};
>
> > + [3] = {
> > + .bus = &mock_pci_bus[3],
> > + },
> > };
> >
> > static bool is_mock_bus(struct pci_bus *bus)
> > @@ -738,6 +781,87 @@ static void mock_companion(struct acpi_device *adev, struct device *dev)
> > #define SZ_512G (SZ_64G * 8)
> > #endif
> >
> > +static __init int cxl_rch_init(void)
> > +{
> > + int rc, i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(cxl_rch); i++) {
> > + int idx = NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + i;
> > + struct acpi_device *adev = &host_bridge[idx];
> > + struct platform_device *pdev;
> > +
> > + pdev = platform_device_alloc("cxl_host_bridge", idx);
> > + if (!pdev)
> > + goto err_bridge;
> > +
> > + mock_companion(adev, &pdev->dev);
> > + rc = platform_device_add(pdev);
> > + if (rc) {
> > + platform_device_put(pdev);
> > + goto err_bridge;
> > + }
> > +
> > + cxl_rch[i] = pdev;
>
> Reason for this suggestion is below.
> Move down cxl_rch[i] = pdev;...
>
> > + mock_pci_bus[idx].bridge = &pdev->dev;
> > + rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj,
> > + "firmware_node");
> > + if (rc)
> > + goto err_bridge;
>
> to here, and clean up this single loop iteration by having a
> platform_device_unregister in the error path above.
Ok, makes sense.
>
> > + }
> > +
> > + for (i = 0; i < ARRAY_SIZE(cxl_rcd); i++) {
> > + int idx = NR_MEM_MULTI + NR_MEM_SINGLE + i;
> > + struct platform_device *rch = cxl_rch[i];
> > + struct platform_device *pdev;
> > +
> > + pdev = platform_device_alloc("cxl_rcd", idx);
> > + if (!pdev)
> > + goto err_mem;
> > + pdev->dev.parent = &rch->dev;
> > + set_dev_node(&pdev->dev, i % 2);
> > +
> > + rc = platform_device_add(pdev);
> > + if (rc) {
> > + platform_device_put(pdev);
> > + goto err_mem;
> > + }
> > + cxl_rcd[i] = pdev;
> > + }
> > +
> > + return 0;
> > +
> > +err_mem:
> > + for (i = ARRAY_SIZE(cxl_rcd) - 1; i >= 0; i--)
> > + platform_device_unregister(cxl_rcd[i]);
> > +err_bridge:
> > + for (i = ARRAY_SIZE(cxl_rch) - 1; i >= 0; i--) {
> > + struct platform_device *pdev = cxl_rch[i];
> > +
> > + if (!pdev)
> > + continue;
> > + sysfs_remove_link(&pdev->dev.kobj, "firmware_node");
>
> Had to look up that this was safe if the file doesn't exist (it is)
> I'd rather not have to check, so maybe make the sysfs path
> above clean up the device in the loop iteration and only set
> cxl_rch[i] once the loop iteration can't fail? See above.
>
> To my mind doing it that way is more 'obviously correct'
> which is never a bad thing.
So this also dovetails with Robert's feedback to move this error exit
block to just call cxl_rch_exit() [1]. In turn both of these feedbacks
are applicable to the other setup loops in this file. So I am thinking
this calls for a follow-on patch to cleanup all the instances of these 2
patterns in this file.
[1]: https://lore.kernel.org/all/Y4ZwXNpwt83puF4W@rric.localdomain/
next prev parent reply other threads:[~2022-12-03 7:50 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 21:33 [PATCH v6 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Dan Williams
2022-12-01 21:33 ` [PATCH v6 01/12] cxl/acpi: Simplify cxl_nvdimm_bridge probing Dan Williams
2022-12-02 15:02 ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 02/12] cxl/region: Drop redundant pmem region release handling Dan Williams
2022-12-02 15:43 ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 03/12] cxl/pmem: Refactor nvdimm device registration, delete the workqueue Dan Williams
2022-12-02 15:42 ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 04/12] cxl/pmem: Remove the cxl_pmem_wq and related infrastructure Dan Williams
2022-12-02 15:44 ` Jonathan Cameron
2022-12-01 21:33 ` [PATCH v6 05/12] cxl/acpi: Move rescan to the workqueue Dan Williams
2022-12-02 15:50 ` Jonathan Cameron
2022-12-03 7:14 ` Dan Williams
2022-12-01 21:33 ` [PATCH v6 06/12] tools/testing/cxl: Make mock CEDT parsing more robust Dan Williams
2022-12-01 21:57 ` Dave Jiang
2022-12-02 15:58 ` Jonathan Cameron
2022-12-03 7:22 ` Dan Williams
2022-12-01 21:33 ` [PATCH v6 07/12] cxl/ACPI: Register CXL host ports by bridge device Dan Williams
2022-12-01 22:00 ` Dave Jiang
2022-12-02 16:11 ` Jonathan Cameron
2022-12-03 7:28 ` Dan Williams
2022-12-01 21:34 ` [PATCH v6 08/12] cxl/acpi: Extract component registers of restricted hosts from RCRB Dan Williams
2022-12-01 23:55 ` Dave Jiang
2022-12-02 8:16 ` Robert Richter
2022-12-03 7:04 ` Dan Williams
2022-12-03 8:41 ` Dan Williams
2022-12-03 16:03 ` Robert Richter
2022-12-03 17:06 ` Dan Williams
2022-12-02 16:38 ` Jonathan Cameron
2022-12-03 7:39 ` Dan Williams
2022-12-01 21:34 ` [PATCH v6 09/12] cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem Dan Williams
2022-12-02 16:40 ` Jonathan Cameron
2022-12-01 21:34 ` [PATCH v6 10/12] cxl/port: Add RCD endpoint port enumeration Dan Williams
2022-12-02 8:21 ` Robert Richter
2022-12-03 7:05 ` Dan Williams
2022-12-02 16:45 ` Jonathan Cameron
2022-12-01 21:34 ` [PATCH v6 11/12] tools/testing/cxl: Add an RCH topology Dan Williams
2022-12-02 8:05 ` Robert Richter
2022-12-02 17:04 ` Jonathan Cameron
2022-12-03 7:50 ` Dan Williams [this message]
2022-12-01 21:34 ` [PATCH v6 12/12] cxl/acpi: Set ACPI's CXL _OSC to indicate RCD mode support Dan Williams
2022-12-02 17:05 ` Jonathan Cameron
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