RE: [PATCH v9 2/3] cxl/acpi: Support CXL XOR Interleave Math (CXIMS)

[Dan Williams <dan.j.williams@intel.com>]

alison.schofield@ wrote:
> From: Alison Schofield <alison.schofield@intel.com>
> 
> When the CFMWS is using XOR math, parse the corresponding
> CXIMS structure and store the xormaps in the root decoder
> structure. Use the xormaps in a new lookup, cxl_hb_xor(),
> to find a targets entry in the host bridge interleave
> target list.
> 
> Defined in CXL Specfication 3.0 Section: 9.17.1
> 
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  drivers/cxl/acpi.c      | 136 +++++++++++++++++++++++++++++++++++++++-
>  drivers/cxl/core/port.c |   9 ++-
>  drivers/cxl/cxl.h       |  11 +++-
>  3 files changed, 148 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index fb649683dd3a..8eee0aa49a77 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
[..]
> @@ -148,7 +265,20 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
>  		ig = CXL_DECODER_MIN_GRANULARITY;
>  	cxld->interleave_granularity = ig;
>  
> +	if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
> +		if (ways != 1 && ways != 3) {
> +			cxims_ctx = (struct cxl_cxims_context) {
> +				.dev = dev,
> +				.cxlrd = cxlrd,
> +			};
> +			rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
> +						   cxl_parse_cxims, &cxims_ctx);
> +			if (rc < 0)
> +				goto err_xormap;

Spotted one question, what about the case there the Window is XOR
arithmetic, but a lookup in the CXIMS comes up empty for the given
granularity? That's certainly a BIOS bug, but BIOSen have been known to
do worse. It would be nice to defend against that potential case with a
follow on fixup, unless I missed it?