Re: [PATCH 3/3] tools/testing/cxl: Document test configurations

[Ira Weiny <ira.weiny@intel.com>]

Jonathan Cameron wrote:
> On Wed, 17 May 2023 14:28:12 -0700
> Ira Weiny <ira.weiny@intel.com> wrote:
> 

[snip]

> > ---
> >  tools/testing/cxl/test/cxl.c | 75 ++++++++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 73 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> > index bf00dc52fe96..bd38a5fb60ae 100644
> > --- a/tools/testing/cxl/test/cxl.c
> > +++ b/tools/testing/cxl/test/cxl.c
> > @@ -23,6 +23,31 @@ static int interleave_arithmetic;
> >  #define NR_CXL_PORT_DECODERS 8
> >  #define NR_BRIDGES (NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + NR_CXL_RCH)
> >  
> > +/*
> > + * Interleave testing
> 
> Doesn't include the cfmws, which will be tricky to draw, but maybe you could
> add something to indicate they interleave over the two HB sometimes?

I was mainly looking to document the devices below.  Because they are all
'platform_device' and they are assigned type in the code which made things
a bit harder for me to follow when I was going through it the other day.

> 
> > + *
> > + *             +---------------+                            +---------------+
> > + *             | host_bridge[0]|                            | host_bridge[1]|
> > + *             +-/---------\---+                            +--/---------\--+
> Text for host bridges is right aligned.

Ah true.  I used an online ascii editor for these.  :-D  So I did not pay
any attention when I copied pasted.

> > + *             /-           -\                               /-           -\
> > + *           /-               -\                           /-               -\
> > + *   +-------------+         +-------------+       +-------------+      +-------------+
> > + *   |root_port[0] |         |root_port[1] |       |root_port[2] |      |root_port[3] |
> > + *   +------|------+         +------|------+       +------|------+      +------|------+
> and root ports are left aligned.
> I'd shrink both boxes so they are same as the switches below - or expand them to give
> a space on either side of the text.

Done.

> >  
> > +/*
> > + * 1) Preconfigured region support (Simulated BIOS configured region)
> > + * 2) 'Pass-through' decoder
> > + *
> > + *       +---------------+
> > + *       |  hb_single    |
> > + *       +------|--------+
> > + *              |
> > + *       +------|--------+
> > + *       | root_single   |
> > + *       +------|--------+
> > + *              |
> > + *   +----------|----------+
> > + *   |     swu_single      |
> > + *   +-----|-----------|---+
> > + *         |           |
> > + *   +-----|-----+  +--|--------+
> > + *   |swd_single |  | swd_single|
> > + *   +-----|-----+  +----|------+
> > + *         |             |
> > + *  +------|-----+  +----|-------+
> > + *  |mem_single  |  |mem_single  |
> > + *  +------------+  +------------+
> mem[0] etc?  Also swd_single[0] etc?
> 
> For consistency with above.
> 

Actually mem_single[0,1].  yea swd_single[0,1].

> >  
> > +/*
> > + *  +---------------+ +---------------+
> > + *  | host_bridge[0]| | host_bridge[1]|
> > + *  +---------------+ +---------------+
> > + *  +---------------+
> > + *  |  hb_single    | (host_bridge[2])
> > + *  +---------------+
> > + *  +-----+
> > + *  | rch | (host_bridge[3])
> > + *  +-----+
> > + */
> 
> Not sure what this diagram is illustrating...

Just showing how the acpi_devices array below ties in with the above
diagrams.  Mainly that their is not a 1:1 corelation between
cxl_host_bridge[] and host_bridge[].  That index 2 and 3 are other
platform devices as shown.

I could probably make that equivalency note in the diagrams above where
hb_single and rch are defined/documented.

Let me do that.
Ira