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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?DIa/LRZznDrlJitk2WLp7M7r+MNB1kthJN5y36oir01BoHd1ytG8N0+J1oIp?= =?us-ascii?Q?s0tyysg8mxPnUSdC4BiAwqOzy2oLa4wL0mqPfWPD0fWd00N5SJtbH9cy+/B1?= =?us-ascii?Q?E0e1B+UC8Ra7M4Ya8QCtlTfC5X1JwoPihsNjjilqrYhwn9nJn63ypbD/FXyO?= =?us-ascii?Q?HwbYA3G07p5hgfQO+TGkJdCqYiDURB6uHdWQYQRHi3UBNZKUegJOovKKYMnq?= =?us-ascii?Q?CR39A3QSLULbIdHJcoV3K6skXdgL+JnJIofeiKB6kM+/nDtc+6jszFYxIl2d?= =?us-ascii?Q?LpWJABSXRMcxT8pW/0p6kWefofKiJXfsm9Q76JENFmI9IzRRxz4gAX2zxh1W?= =?us-ascii?Q?aJqqfwjfAp8DcPUX2haTpzd0JyDRd9PumirLoWDpMwJfCtpokxe+kdQgj+pN?= =?us-ascii?Q?QwCLNWzC2vbJB1LgFROKmpGEzENaSTFMn5NmpwMzD6M7RNakucTXk4Tyg+w/?= =?us-ascii?Q?bEhbHmiFfuH9mU85bTN8eKMAMj4TA01MlnIR4HFzaQxrg316eA6krVSOUSkb?= =?us-ascii?Q?owGOrIiv5vidvmn++UgAyG7WWbVGfxerY+TNJlMG6S0qnBWl5jnyVsCJUC30?= =?us-ascii?Q?2Tv6Yeu/XOmVq4Wl0s56G5J/7Uxrjb503MBMkj0bwWWrf5znXAXZBvndNOYl?= =?us-ascii?Q?K4cjxwlHbt7VNFbWVa4RzFBf9wIFp1J5SrYPje4mK5lfYGZS2BcmzhFstPxF?= =?us-ascii?Q?Er6trl347dcfkXIUrmoEgbXVvcMIGg+PtAv4i1m/rzq8KXHPm5dReWzj6mtI?= =?us-ascii?Q?sAhXCXkoIXDyMYxMXRV4ogvfFvpCHd3v5n3jupZpQzR+MYy8Q7356LHN54ig?= =?us-ascii?Q?f1an14ZPa32S9QN8TIJJAd6KqO654FdL62AORo/GU5CQ4n4wMvneV/3s/bPK?= =?us-ascii?Q?5d+xTpoPIePFa/v734AzBZgJPqp+252GrPzOhNkFCkjeS4R9+LS3xknyHrew?= =?us-ascii?Q?xhPusUegCBrS8dqFICpAuzb8AnsP/BPoKMIUlXxmDQvaqwyOOdST347Fw75B?= =?us-ascii?Q?5Zitu17yS3IloeuX4JLNHcTCLQLOP41xbd6dqwdvCTLgFgcB+uNh41uP6d1t?= =?us-ascii?Q?JRwMFqPPBgz/UnuX9dVVkuvWlE97SAyx33urcn1PSVs1EEuQ0fMqLn0MGB2T?= =?us-ascii?Q?tu3eR7GTN8s7UDNhyDkc3o5PGaAS6O7T1WRe1Qva2qWQJb9Z81yD57KLN9UQ?= =?us-ascii?Q?rL73ZU6toP547uC8ziL92o2gDiNIl74c7oH56SJ7AV6LoFxGY5e71zxZu9sp?= =?us-ascii?Q?/9WU59eMQ+8WvSFFAD03sJK3je6Uq4JsfwHl3em4YZAYIIq7Aa/hQ5BczyIX?= =?us-ascii?Q?hPbPLnFKNlZttXOuLccypWZk1SpZ//YdfHp9QNeMSaP/cUtx0kmxuHyrE529?= =?us-ascii?Q?0emK3CrEkL8NHk/DOnWkWb/ZFz9UJjRf2Gt7SlE1vHH7k7sNtYzX1jN9nCtn?= =?us-ascii?Q?E5tP3t9eWv76c/5GdII2n6NhDyVpHaPImJg0fbJpJ5jeaRfXn9zvLIlv7biI?= =?us-ascii?Q?wRNDX4TQCL+K/JK4kT5KwhlbNhWz5SomHvgBEi5atnWHECzSWDeCUmfUN+9Q?= =?us-ascii?Q?6lxBwMBOrkrwtraGq1BNRc0CN94rMK/SRzfeopd5fKlJjoAiNbWtpRMI9Oih?= =?us-ascii?Q?xA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 0ce0753b-432e-411f-674c-08dbb582914d X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 00:27:39.3601 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TbluOnXNyBnnq3ee7nf282lrecoGRHJAUn63uyJH+5/2teJhMrbTlM4xsBqvlJHV7aRxRAs6U28BzoAvLcS1/Q28+0ODn0WaX41/BM84ynQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR11MB7597 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Terry Bowman wrote: > The restricted CXL host (RCH) error handler will log protocol errors > using AER and RAS status registers. The AER and RAS registers need > to be virtually memory mapped before enabling interrupts. Update > __devm_cxl_add_dport() to include RCH RAS and AER mapping. > > Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to > the RCH downstream port's AER and RAS registers. > > Co-developed-by: Robert Richter > Signed-off-by: Robert Richter > Signed-off-by: Terry Bowman > Reviewed-by: Jonathan Cameron > Reviewed-by: Dave Jiang > --- > drivers/cxl/core/port.c | 34 ++++++++++++++++++++++++++++++++++ > drivers/cxl/core/regs.c | 1 + > drivers/cxl/cxl.h | 12 ++++++++++++ > 3 files changed, 47 insertions(+) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 45f8846d8c8a..2a22a7ed4704 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -949,6 +950,37 @@ static void cxl_dport_unlink(void *data) > sysfs_remove_link(&port->dev.kobj, link_name); > } > > +static void cxl_dport_map_rch_aer(struct cxl_dport *dport) > +{ > + struct cxl_rcrb_info *ri = &dport->rcrb; > + struct cxl_port *port = dport->port; > + void __iomem *dport_aer = NULL; > + resource_size_t aer_phys; > + > + if (dport->rch && ri->aer_cap) { > + aer_phys = ri->aer_cap + ri->base; > + dport_aer = devm_cxl_iomap_block(&port->dev, aer_phys, > + sizeof(struct aer_capability_regs)); > + } > + > + dport->regs.dport_aer = dport_aer; > +} > + > +static void cxl_dport_map_regs(struct cxl_dport *dport) > +{ > + struct cxl_register_map *map = &dport->comp_map; > + struct device *dev = dport->dport_dev; > + > + if (!map->component_map.ras.valid) > + dev_dbg(dev, "RAS registers not found\n"); > + else if (cxl_map_component_regs(map, dev, &dport->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS))) > + dev_dbg(dev, "Failed to map RAS capability.\n"); > + > + if (dport->rch) > + cxl_dport_map_rch_aer(dport); > +} > + > static struct cxl_dport * > __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, > int port_id, resource_size_t component_reg_phys, > @@ -1008,6 +1040,8 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, > if (rc) > return ERR_PTR(rc); > > + cxl_dport_map_regs(dport); > + Mapping registers for usage is a driver operation, not an enumeration operation, so this should move out of add_dport, and it should fail the driver load if it fails. Yes this happens to be the case that dports are only enumerated in cxl_port driver probe path, but that need not be the case forever and no other parts of the CXL core are lighting up registers from an enumeration routine.