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From: Dan Williams <dan.j.williams@intel.com>
To: Gregory Price <gregory.price@memverge.com>,
	Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
	<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
	<alison.schofield@intel.com>, <Jonathan.Cameron@huawei.com>,
	<dave@stgolabs.net>
Subject: Re: [PATCH v11 20/22] cxl: Store QTG IDs and related info to the CXL memory device context
Date: Fri, 27 Oct 2023 21:23:40 -0700	[thread overview]
Message-ID: <653c8ccc68787_244c8f29495@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <ZTvwxkOg3WCW6RFd@memverge.com>

Gregory Price wrote:
> On Thu, Oct 12, 2023 at 11:55:30AM -0700, Dave Jiang wrote:
> > Once the QTG ID _DSM is executed successfully, the QTG ID is retrieved from
> > the return package. Create a list of entries in the cxl_memdev context and
> > store the QTG ID as qos_class token and the associated DPA range. This
> > information can be exposed to user space via sysfs in order to help region
> > setup for hot-plugged CXL memory devices.
> > 
> > Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> > 
> [... snip ...]
> >  static int cxl_switch_port_probe(struct cxl_port *port)
> >  {
> >  	struct cxl_hdm *cxlhdm;
> > @@ -196,17 +239,22 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
> >  		rc = cxl_cdat_endpoint_process(port, &dsmas_list);
> >  		if (rc < 0) {
> >  			dev_dbg(&port->dev, "Failed to parse CDAT: %d\n", rc);
> > -		} else {
> > -			rc = cxl_port_perf_data_calculate(port, &dsmas_list);
> > -			if (rc)
> > -				dev_dbg(&port->dev,
> > -					"Failed to do perf coord calculations.\n");
> > +			goto out;
> >  		}
> >  
> > +		rc = cxl_port_perf_data_calculate(port, &dsmas_list);
> > +		if (rc) {
> > +			dev_dbg(&port->dev,
> > +				"Failed to do perf coord calculations.\n");
> > +			goto out;
> > +		}
> > +
> > +		cxl_memdev_set_qos_class(cxlds, &dsmas_list);
> > +out:
> >  		cxl_cdat_dsmas_list_destroy(&dsmas_list);
> >  	}
> >  
> > -	return 0;
> > +	return rc;
> >  }
> 
> This causes existing devices which do not have _DSM implemented to fail
> to map without this QoS extension.  Please consider having the
> cxl_switch_port_probe function return 0 even if the QoS changes here
> fail so that existing expander mapping continues to work.
> 
> I presume future QEMU implementations will have the appropriate _DSM
> acpi field, but older ones do not.

I'll drop that error return for now.

  reply	other threads:[~2023-10-28  4:23 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-12 18:53 [PATCH v11 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-10-12 18:53 ` [PATCH v11 01/22] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute Dave Jiang
2023-10-12 18:53 ` [PATCH v11 02/22] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-10-12 18:53 ` [PATCH v11 03/22] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-10-12 18:53 ` [PATCH v11 04/22] acpi: Move common tables helper functions to common lib Dave Jiang
2023-10-12 18:54 ` [PATCH v11 05/22] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-10-12 18:54 ` [PATCH v11 06/22] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-10-28  4:51   ` Dan Williams
2023-10-12 18:54 ` [PATCH v11 07/22] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-10-12 18:54 ` [PATCH v11 08/22] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-10-12 18:54 ` [PATCH v11 09/22] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-10-12 18:54 ` [PATCH v11 10/22] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-10-12 18:54 ` [PATCH v11 11/22] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-10-12 18:54 ` [PATCH v11 12/22] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-10-28  4:08   ` Dan Williams
2023-10-12 18:54 ` [PATCH v11 13/22] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-10-12 18:54 ` [PATCH v11 14/22] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-10-12 18:55 ` [PATCH v11 15/22] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-10-16 10:56   ` Jonathan Cameron
2023-10-12 18:55 ` [PATCH v11 16/22] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 17/22] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 18/22] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 19/22] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-10-12 18:55 ` [PATCH v11 20/22] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-10-16 10:58   ` Jonathan Cameron
2023-10-27  4:48   ` Gregory Price
2023-10-27 17:17   ` Gregory Price
2023-10-28  4:23     ` Dan Williams [this message]
2023-10-12 18:55 ` [PATCH v11 21/22] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-10-16 10:59   ` Jonathan Cameron
2023-10-12 18:55 ` [PATCH v11 22/22] cxl: Check qos_class validity on memdev probe Dave Jiang
2023-10-16 11:04   ` Jonathan Cameron
2023-10-28  4:29     ` Dan Williams
2023-10-26 22:54 ` [PATCH v11 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Gregory Price
2023-10-30 16:18   ` Dave Jiang

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