From: Dan Williams <dan.j.williams@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
<dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<dave@stgolabs.net>, Bjorn Helgaas <bhelgaas@google.com>
Subject: RE: [PATCH v15 12/19] cxl: Calculate and store PCI link latency for the downstream ports
Date: Fri, 22 Dec 2023 15:31:24 -0800 [thread overview]
Message-ID: <65861c4cb2fff_2581a29433@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <170319621931.2212653.6800240203604822886.stgit@djiang5-mobl3>
[ add Bjorn for the new changes to drivers/pci/pci.c ]
Dave Jiang wrote:
> The latency is calculated by dividing the flit size over the bandwidth. Add
> support to retrieve the flit size for the CXL switch device and calculate
> the latency of the PCIe link. Cache the latency number with cxl_dport.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/core.h | 2 +
> drivers/cxl/core/pci.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++
> drivers/cxl/core/port.c | 6 ++++
> drivers/cxl/cxl.h | 4 +++
> drivers/cxl/cxlpci.h | 13 ++++++++
> 5 files changed, 97 insertions(+)
>
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 86d7ba23235e..3b64fb1b9ed0 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -88,4 +88,6 @@ enum cxl_poison_trace_type {
> CXL_POISON_TRACE_CLEAR,
> };
>
> +long cxl_pci_get_latency(struct pci_dev *pdev);
> +
> #endif /* __CXL_CORE_H__ */
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index eff20e83d0a6..a014d49d2f12 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -1,5 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
> +#include <linux/units.h>
> #include <linux/io-64-nonatomic-lo-hi.h>
> #include <linux/device.h>
> #include <linux/delay.h>
> @@ -980,3 +981,74 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
> return PCI_ERS_RESULT_NEED_RESET;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_error_detected, CXL);
> +
> +extern const unsigned char pcie_link_speed[];
Checkpatch complains about this definition:
WARNING: externs should be avoided in .c files
#48: FILE: drivers/cxl/core/pci.c:984:
...and really it's a PCI core internal that others outside of the PCI
core should not care about.
> +static enum pci_bus_speed get_link_speed(struct pci_dev *pdev)
> +{
> + u16 linkstat;
> + int err;
> +
> + err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &linkstat);
> + if (err)
> + return -EINVAL;
> +
> + return pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS];
> +}
> +
> +static int pci_bus_speed_to_mbps(enum pci_bus_speed speed)
> +{
> + switch (speed) {
> + case PCIE_SPEED_2_5GT:
> + return 2500;
> + case PCIE_SPEED_5_0GT:
> + return 5000;
> + case PCIE_SPEED_8_0GT:
> + return 8000;
> + case PCIE_SPEED_16_0GT:
> + return 16000;
> + case PCIE_SPEED_32_0GT:
> + return 32000;
> + case PCIE_SPEED_64_0GT:
> + return 64000;
> + default:
> + break;
> + }
> +
> + return -EINVAL;
> +}
This looks like pure PCI core material, not anything CXL specific, lets
move it where it belongs.
Will fold this incremental change, Bjorn please holler if you have
objections, otherwise I will start this soaking in linux-next.
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 7551dee1c7b0..6c9c8d92f8f7 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -981,42 +981,6 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
}
EXPORT_SYMBOL_NS_GPL(cxl_error_detected, CXL);
-extern const unsigned char pcie_link_speed[];
-
-static enum pci_bus_speed get_link_speed(struct pci_dev *pdev)
-{
- u16 linkstat;
- int err;
-
- err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &linkstat);
- if (err)
- return -EINVAL;
-
- return pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS];
-}
-
-static int pci_bus_speed_to_mbps(enum pci_bus_speed speed)
-{
- switch (speed) {
- case PCIE_SPEED_2_5GT:
- return 2500;
- case PCIE_SPEED_5_0GT:
- return 5000;
- case PCIE_SPEED_8_0GT:
- return 8000;
- case PCIE_SPEED_16_0GT:
- return 16000;
- case PCIE_SPEED_32_0GT:
- return 32000;
- case PCIE_SPEED_64_0GT:
- return 64000;
- default:
- break;
- }
-
- return -EINVAL;
-}
-
static int cxl_flit_size(struct pci_dev *pdev)
{
if (cxl_pci_flit_256(pdev))
@@ -1044,7 +1008,7 @@ long cxl_pci_get_latency(struct pci_dev *pdev)
{
long bw;
- bw = pci_bus_speed_to_mbps(get_link_speed(pdev));
+ bw = pcie_link_speed_mbps(pdev);
if (bw < 0)
return 0;
bw /= BITS_PER_BYTE;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 55bc3576a985..00817d403ad4 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -6224,6 +6224,41 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
}
EXPORT_SYMBOL(pcie_set_mps);
+static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
+{
+ return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
+}
+
+int pcie_link_speed_mbps(struct pci_dev *pdev)
+{
+ u16 lnksta;
+ int err;
+
+ err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
+ if (err)
+ return err;
+
+ switch (to_pcie_link_speed(lnksta)) {
+ case PCIE_SPEED_2_5GT:
+ return 2500;
+ case PCIE_SPEED_5_0GT:
+ return 5000;
+ case PCIE_SPEED_8_0GT:
+ return 8000;
+ case PCIE_SPEED_16_0GT:
+ return 16000;
+ case PCIE_SPEED_32_0GT:
+ return 32000;
+ case PCIE_SPEED_64_0GT:
+ return 64000;
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(pcie_link_speed_mbps);
+
/**
* pcie_bandwidth_available - determine minimum link settings of a PCIe
* device and its bandwidth limitation
@@ -6257,8 +6292,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
while (dev) {
pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
- next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS,
- lnksta)];
+ next_speed = to_pcie_link_speed(lnksta);
next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index dea043bc1e38..504a4ba2c29e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1364,6 +1364,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps);
u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
enum pci_bus_speed *speed,
enum pcie_link_width *width);
+int pcie_link_speed_mbps(struct pci_dev *pdev);
void pcie_print_link_status(struct pci_dev *dev);
int pcie_reset_flr(struct pci_dev *dev, bool probe);
int pcie_flr(struct pci_dev *dev);
next prev parent reply other threads:[~2023-12-22 23:31 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-21 22:02 [PATCH v15 00/19] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-12-21 22:02 ` [PATCH v15 01/19] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-12-21 22:02 ` [PATCH v15 02/19] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-12-21 22:02 ` [PATCH v15 03/19] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-12-21 22:02 ` [PATCH v15 04/19] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-12-21 22:02 ` [PATCH v15 05/19] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-12-21 22:03 ` [PATCH v15 06/19] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-12-21 22:03 ` [PATCH v15 07/19] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-12-21 22:03 ` [PATCH v15 08/19] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-12-21 22:03 ` [PATCH v15 09/19] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-12-21 22:03 ` [PATCH v15 10/19] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-12-21 22:03 ` [PATCH v15 11/19] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-12-21 22:03 ` [PATCH v15 12/19] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-12-22 23:31 ` Dan Williams [this message]
2023-12-21 22:03 ` [PATCH v15 13/19] tools/testing/cxl: Add hostbridge UID string for cxl_test mock hb devices Dave Jiang
2023-12-21 22:03 ` [PATCH v15 14/19] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-12-21 22:03 ` [PATCH v15 15/19] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-12-21 22:04 ` [PATCH v15 16/19] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-12-21 22:04 ` [PATCH v15 17/19] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-12-21 22:04 ` [PATCH v15 18/19] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-12-21 22:04 ` [PATCH v15 19/19] cxl: Check qos_class validity on memdev probe Dave Jiang
2024-01-04 13:19 ` Robert Richter
2024-01-04 16:12 ` Dave Jiang
2023-12-29 0:04 ` [PATCH v15 00/19] cxl: Add support for QTG ID retrieval for CXL subsystem Bjorn Helgaas
2024-01-04 1:00 ` Dan Williams
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